MC9S08QG8CDTER Freescale, MC9S08QG8CDTER Datasheet - Page 83

• Manufacturer Part Number: MC9S08QG8CDTER
• Manufacturer: Freescale

Specifications of MC9S08QG8CDTER

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 512Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Lead Free Status / RoHS Status: Compliant

1
1
6.4.2.1
An internal pullup device can be enabled for each port pin by setting the corresponding bit in the pullup
enable register (PTAPEn). The pullup device is disabled if the pin is configured as an output by the parallel
I/O control logic or any shared peripheral function regardless of the state of the corresponding pullup
enable register bit. The pullup device is also disabled if the pin is controlled by an analog function.
6.4.2.2
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTASEn). When enabled, slew control limits the rate at which an output can transition to reduce
EMC emissions. Slew rate control has no effect on pins which are configured as inputs.
Freescale Semiconductor
PTAPE[5:0]
PTASE[5:0]
Reset:
PTAPE4 has no effect on the output-only PTA4 pin.
Reset:
PTASE5 has no effect on the input-only PTA5 pin.
Field
Field
5:0
5:0
W
W
R
R
Internal Pullup Enable for Port A Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port A bit n.
1 Internal pullup device enabled for port A bit n.
Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
Port A Internal Pullup Enable (PTAPE)
0
Port A Slew Rate Enable (PTASE)
0
7
0
7
0
Figure 6-4. Internal Pullup Enable for Port A Register (PTAPE)
Figure 6-6. Slew Rate Enable for Port A Register (PTASE)
0
0
0
0
6
6
Table 6-3. PTAPE Register Field Descriptions
Table 6-4. PTASE Register Field Descriptions
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
PTASE5
PTAPE5
0
1
5
5
1
PTAPE4
PTASE4
0
1
4
4
Description
Description
1
PTAPE3
PTASE3
3
0
3
1
PTAPE2
PTASE2
Chapter 6 Parallel Input/Output Control
0
1
2
2
PTAPE1
PTASE1
0
1
1
1
PTAPE0
PTASE0
0
1
0
0
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