ALXD800EEXJ2VD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD C3 Datasheet - Page 116

• Manufacturer Part Number: ALXD800EEXJ2VD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

116
27:25
23:21
19:17
Bit
28
24
20
16
15
14
13
12
11
10
9
8
7
Name
II_NS
RSVD
CC_SER
RSVD
RQ_SER
RSVD
II_SER
RSVD
II_IMFLSH
RSVD
CC_L0
RSVD
DMM_DIS
RSVD
CC_PS
RSVD
33234H
Description
Instruction Pipeline (IP) Empty Mode.
0: IM Interface may make requests to Instruction Memory (IM) when the IP is not empty.
(Default)
1: IM Interface only makes requests to IM after the IP is empty.
Note:
Reserved.
COF Cache Serialization.
0: Allow more than one outstanding request in COF cache. (Default)
1: Allow only one request in the COF cache.
Note:
Reserved.
Request Queue Serialization.
0: Allow more than one request in the Request Queue. (Default)
1: Only one request is allowed in the Request Queue.
Note:
Reserved.
Instruction Memory Request Serialization.
0: IM requests are not serialized. (Default)
1: IM Interface waits until IM responds to a request before IM Interface issues the next
request.
Note:
Reserved.
Instruction Memory Flush.
0: IF never issues flush requests to IM.
1: IF may issue flush requests to IM. (Default)
Note:
Reserved.
Level-0 COF Cache.
0: Disable.
1: Enable. (Default)
Note:
Reserved.
Debug Management Mode (DMM).
0: The COF cache and return stack is neither used nor updated during DMM. (Default)
1: The COF cache and return stack may be used and updated during DMM.
Note:
Reserved.
Power Saving Mode.
0: Disable. (Default)
1: Enable.
Note:
Reserved.
IF_CONFIG_MSR Bit Descriptions (Continued)
Enabling this mode reduces performance.
Enabling COF cache serialization may reduce performance.
Enabling RQ serialization reduces performance.
Enabling IM Interface serialization reduces performance.
Enabling IM flushing usually increases performance.
Enabling the L0 COF cache increases performance. Unless CC_L1 is enabled
(bit 0 = 1), then CC_L0 has no effect.
Disabling the COF cache and return stack during DMM may reduce performance
but make debug easier.
CC_L1 must be disabled (bit 0 = 0) to enable power saving.
AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions