ALXD800EEXJ2VD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD C3 Datasheet - Page 354

• Manufacturer Part Number: ALXD800EEXJ2VD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.6.15.2 DC CRT Vertical Blank Timing for Even Fields (DC_V_BLANK_EVEN_TIMING)
DC Memory Offset 0E8h
Type
Reset Value
This register contains vertical blank timing information. All values are specified in lines. This register is used ONLY for even
fields in interlaced display modes. Settings written to this register do not take effect until the start of the frame or interlaced
field after the timing register update bit is set (DC Memory Offset 008h[6] = 1).
6.6.15.3 DC CRT Vertical Sync Timing for Even Fields (DC_V_SYNC_EVEN_TIMING)
DC Memory Offset 0ECh
Type
Reset Value
This register contains CRT vertical sync timing information. All values are specified in lines. This register is used ONLY for
even fields in interlaced modes. Settings written to this register do not take effect until the start of the frame or interlaced
field after the timing register update bit is set (DC Memory Offset 008h[6] = 1).
354
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:27
26:16
15:11
31:27
26:16
15:11
10:0
10:0
Bit
Bit
RSVD
RSVD
Name
RSVD
V_BLANK_END
RSVD
V_BLANK_
Name
RSVD
V_SYNC_END
RSVD
V_SYNC_
START
START
R/W
xxxxxxxxh
R/W
xxxxxxxxh
33234H
Description
Reserved. These bits should be programmed to zero.
Vertical Blank End. This field represents the line at which the vertical blanking signal
becomes inactive minus 1. If the display is interlaced, no border is supported, so this
value should be identical to V_TOTAL (DC Memory Offset 0E4h[26:16]).
Reserved. These bits should be programmed to zero.
Vertical Blank Start. This field represents the line at which the vertical blanking signal
becomes active minus 1. If the display is interlaced, this value should be programmed to
V_ACTIVE (DC Memory Offset 0E4h[10:0]) plus 1.
Description
Reserved. These bits should be programmed to zero.
Vertical Sync End. This field represents the line at which the CRT vertical sync signal
becomes inactive minus 1.
Reserved. These bits should be programmed to zero.
Vertical Sync Start. This field represents the line at which the CRT vertical sync signal
becomes active minus 1. For interlaced display, note that the vertical counter is incre-
mented twice during each line and since there are an odd number of lines, the vertical
sync pulse will trigger in the middle of a line for one field and at the end of a line for the
subsequent field.
V_BLANK_END
DC_V_BLANK_EVEN_TIMING Bit Descriptions
V_SYNC_END
DC_V_SYNC_EVEN_TIMING Bit Descriptions
DC_V_BLANK_EVEN_TIMING Register Map
DC_V_SYNC_EVEN_TIMING Register Map
RSVD
RSVD
Display Controller Register Descriptions
AMD Geode™ LX Processors Data Book
9
9
8
8
7
V_BLANK_START
7
V_SYNC_START
6
6
5
5
4
4
3
3
2
2
1
1
0
0