IDT82V3285DQ IDT, Integrated Device Technology Inc, IDT82V3285DQ Datasheet
IDT82V3285DQ
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IDT82V3285DQ Summary of contents
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WAN PLL IDT82V3285 Version - April 11, 2007 6024 Silver Creek Valley Road, San Jose, CA 95138 Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775 Printed in U.S.A. © 2006 Integrated Device Technology, Inc. ...
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Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos- sible product. IDT does not assume any ...
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FEATURES .............................................................................................................................................................................. 9 HIGHLIGHTS.................................................................................................................................................................................................... 9 MAIN FEATURES ............................................................................................................................................................................................ 9 OTHER FEATURES ......................................................................................................................................................................................... 9 APPLICATIONS....................................................................................................................................................................... 9 DESCRIPTION....................................................................................................................................................................... 10 FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11 1 PIN ASSIGNMENT ........................................................................................................................................................... 12 2 PIN DESCRIPTION .......................................................................................................................................................... 13 3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 18 3.1 RESET ........................................................................................................................................................................................................... ...
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IDT82V3285 3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 32 3.10.1.5 Holdover Mode ................................................................................................................................................................. 32 3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 33 3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 33 3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 33 3.10.1.5.4 Manual ........................................................................................................................................................... 33 3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 33 3.10.1.6 ...
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IDT82V3285 8.3 HEATSINK EVALUATION .......................................................................................................................................................................... 127 9 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 128 9.1 ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 128 9.2 RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 128 9.3 I/O SPECIFICATIONS ................................................................................................................................................................................. 129 9.3.1 CMOS Input / Output Port ............................................................................................................................................................ 129 9.3.2 PECL / LVDS ...
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Table 1: Pin Description ............................................................................................................................................................................................. 13 Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 18 Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 19 Table 4: Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 20 Table ...
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IDT82V3285 Table 49: CMOS Output Port Electrical Characteristics ............................................................................................................................................ 129 Table 50: PECL Input / Output Port Electrical Characteristics ................................................................................................................................... 131 Table 51: LVDS Input / Output Port Electrical Characteristics ................................................................................................................................... 132 Table 52: Output Clock Jitter Generation .................................................................................................................................................................. 133 ...
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Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11 Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 12 Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 20 Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 21 Figure 5. External Fast Selection ................................................................................................................................................................................ 23 Figure ...
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FEATURES HIGHLIGHTS • The first single PLL chip: • Features 0.5 mHz to 560 Hz bandwidth • Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/ Option I) jitter generation requirements • Provides node clocks for Cellular and WLL base-station (GSM and ...
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IDT82V3285 DESCRIPTION The IDT82V3285 is an integrated, single-chip solution for the Syn- chronous Equipment Timing Source for Stratum 2, 3E, 3, SMC, 4E and 4 clocks in SONET / SDH equipments, DWDM and Wireless base station, such as GSM, 3G, ...
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IDT82V3285 FUNCTIONAL BLOCK DIAGRAM Functional Block Diagram Figure 1. Functional Block Diagram 11 WAN PLL April 11, 2007 ...
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IDT82V3285 1 PIN ASSIGNMENT 1 AGND 2 TRST 3 IC1 4 IC2 5 AGND1 6 VDDA1 7 TMS 8 INT_REQ 9 TCK 10 OSCI 11 DGND1 12 VDDD1 13 VDDD3 14 DGND3 15 DGND2 VDDD2 16 17 IC3 18 FF_SRCSW ...
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IDT82V3285 2 PIN DESCRIPTION Table 1: Pin Description Name Pin No. OSCI 10 FF_SRCSW 18 MS/SL 99 SONET/SDH 100 74 RST EX_SYNC1 45 IN1 46 IN2 47 IN3_POS 40 IN3_NEG 41 IN4_POS 42 IN4_NEG 43 Pin Description I/O Type Global ...
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IDT82V3285 Table 1: Pin Description (Continued) Name Pin No. IN5 54 FRSYNC_8K 30 MFRSYNC_2K 31 OUT1 90 OUT2 93 OUT3 94 OUT4_POS 34 OUT4_NEG 35 OUT5_POS 36 OUT5_NEG INT_REQ 8 Pin Description I/O Type IN5: Input Clock ...
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IDT82V3285 Table 1: Pin Description (Continued) Name Pin No. MPU_MODE0 60 MPU_MODE1 59 MPU_MODE2 SDI CLKE AD0 / SDO 83 AD1 82 AD2 ...
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IDT82V3285 Table 1: Pin Description (Continued) Name Pin No. ALE / SCLK 73 RDY 75 TRST 2 TMS 7 TCK 9 TDI 23 TDO 21 VDDD1 12 VDDD2 16 VDDD3 13 VDDD4 50 VDDD5 61 VDDD6 85 VDDD7 86 Pin ...
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IDT82V3285 Table 1: Pin Description (Continued) Name Pin No. VDDA1 6 VDDA2 19 VDDA3 91 VDDD8 26 VDD_DIFF1 33 VDD_DIFF2 39 DGND1 11 DGND2 15 DGND3 14 DGND4 49 DGND5 62 DGND6 84 DGND7 87 AGND1 5 AGND2 20 AGND3 ...
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IDT82V3285 3 FUNCTIONAL DESCRIPTION 3.1 RESET The reset operation resets all registers and state machines to their default value or status. After power on, the device must be reset for normal operation. For a complete reset, the RST pin must ...
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IDT82V3285 3.3 INPUT CLOCKS & FRAME SYNC SIGNAL Altogether 5 clocks and 1 frame sync signal are input to the device. 3.3.1 INPUT CLOCKS The device provides 5 input clock ports. According to the input port technology, the input ports ...
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IDT82V3285 3.4 INPUT CLOCK PRE-DIVIDER Each input clock is assigned an internal Pre-Divider. The Pre-Divider is used to divide the clock frequency down to the DPLL required fre- quency, which is no more than 38.88 MHz. For IN1 ~ IN5, ...
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IDT82V3285 3.5 INPUT CLOCK QUALITY MONITORING The qualities of all the input clocks are always monitored in the fol- lowing aspects: • Activity • Frequency Activity and frequency monitoring are conducted on all the input clocks. The qualified clocks are ...
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IDT82V3285 3.5.2 FREQUENCY MONITORING Frequency is monitored by comparing the input clock with a refer- ence clock. The reference clock can be derived from the master clock or the output of T0 DPLL, as determined by the FREQ_MON_CLK bit. A ...
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IDT82V3285 3 DPLL INPUT CLOCK SELECTION An input clock is selected for T0 DPLL and for T4 DPLL respectively. For T0 path, the EXT_SW bit and the T0_INPUT_SEL[3:0] bits deter- mine the input clock selection, as shown ...
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IDT82V3285 3.6.2 FORCED SELECTION In Forced selection, the selected input clock is set by the T0_INPUT_SEL[3:0] / T4_INPUT_SEL[3:0] bits. The results of input clocks quality monitoring (refer to Chapter 3.5 Input Clock Quality Moni- toring) do not affect the input ...
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IDT82V3285 3.7 SELECTED INPUT CLOCK MONITORING The quality of the selected input clock is always monitored (refer to Chapter 3.5 Input Clock Quality Monitoring) and the DPLL locking status is always monitored. 3.7 DPLL LOCKING DETECTION The ...
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IDT82V3285 3.7.3 PHASE LOCK ALARM (T0 ONLY) A phase lock alarm will be raised when the selected input clock can not be locked in T0 DPLL within a certain period. This period can be cal- culated as follows: Period (sec.) ...
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IDT82V3285 3.8 SELECTED INPUT CLOCK SWITCH If the input clock is selected by External Fast selection or by Forced selection, it can be switched by setting the related registers (refer to Chapter 3.6.1 External Fast Selection (T0 only) Selection) any ...
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IDT82V3285 3.8.2.2 Non-Revertive Switch (T0 only) In Non-Revertive switch, the T0 selected input clock is not switched when another qualified input clock with a higher priority than the current selected input clock is available. In this case, the selected input ...
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IDT82V3285 3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE The operating modes supported by T0 DPLL are more complex than the ones supported by T4 DPLL for T0 path is the main one. T0 DPLL supports three primary operating ...
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IDT82V3285 15 Figure 7. T0 Selected Input Clock vs. DPLL Automatic Operating Mode Notes to Figure 7: 1. Reset input clock is selected. 3. The T0 selected input clock is disqualified AND No qualified input clock is available. ...
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IDT82V3285 The causes of Item ‘the T0 selected input clock is switched to another one’ - are: (The T0 selected input clock is disquali- fied AND Another input clock is switched to) OR (In Revertive ...
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IDT82V3285 3. DPLL OPERATING MODE The T0/T4 DPLL gives a stable performance in different applications without being affected by operating conditions or silicon process varia- tions. It integrates a PFD (Phase & Frequency Detector), a LPF (Low ...
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IDT82V3285 phase locked to any input clock. The frequency offset acquiring method is selected by the MAN_HOLDOVER bit, the AUTO_AVG bit and the FAST_AVG bit, as shown in Table 19: Table 19: Frequency Offset Control in Holdover Mode MAN_HOLDOVER AUTO_AVG ...
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IDT82V3285 phase locked to any input clock. The T4 DPLL freezes at the operating frequency when it enters Holdover mode. The accuracy is 4.4X10 ppm. Table 21: Related Bit / Register in Chapter 3.10 Bit CURRENT_PH_DATA[15:0] CURRENT_DPLL_FREQ[23:0] T0_DPLL_START_BW[4:0] T0_DPLL_START_DAMPING[2:0] T0_DPLL_ACQ_BW[4:0] ...
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IDT82V3285 3. DPLL OUTPUT The DPLL output is locked to the selected input clock. According to the phase-compared result of the feedback and the selected input clock, and the DPLL output frequency offset, the PFD output is ...
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IDT82V3285 3.11.5.2 T4 Path The four paths for T4 DPLL output are as follows: • 77.76 MHz path - outputs a 77.76 MHz clock; • 16E1/16T1 path - outputs a 16E1 or 16T1 clock, as selected by the IN_SONET_SDH bit; ...
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IDT82V3285 3. APLL A T0 APLL and a T4 APLL are provided for a better jitter and wander performance of the device output clocks. The bandwidths of the T0/T4 APLL are set by the T0_APLL_BW[1:0] / T4_APLL_BW[1:0] ...
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IDT82V3285 Table 25: Outputs on OUT1 ~ OUT5 if Derived from T0/T4 APLL OUTn_DIVIDER[3:0] 1 (Output Divider) 77.76 MHz X 4 12E1 X 4 0000 3 0001 622.08 MHz 3 0010 48E1 311.04 MHz 0011 155.52 MHz 24E1 0100 77.76 ...
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IDT82V3285 3.13.2 FRAME SYNC OUTPUT SIGNALS An 8 kHz and a 2 kHz frame sync signals are output on the FRSYNC_8K and MFRSYNC_2K pins if enabled by the 8K_EN and 2K_EN bits respectively. They are CMOS outputs. The two frame ...
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IDT82V3285 T0 selected input clock EX_SYNC1 Frame sync output signals Output clocks Figure 11. 0.5 UI Late Frame Sync Input Signal Timing Table 27: Related Bit / Register in Chapter 3.13 Bit OUT4_PECL_LVDS OUT5_PECL_LVDS OUTn_PATH_SEL[3:0] (1 ≤ n ≤ 5) ...
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IDT82V3285 3.14 MASTER / SLAVE CONFIGURATION Master / Slave configuration is only supported by the T0 path of the device. Two devices should be used together in order to: • Enable system protection against single chip failure; • Guarantee no ...
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IDT82V3285 3.15 INTERRUPT SUMMARY The interrupt sources of the device are as follows: • T4 DPLL locking status change • Input clocks for T0 path validity change • T0 selected input clock fail • No qualified input clock for T4 ...
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IDT82V3285 3.17 POWER SUPPLY FILTERING TECHNIQUES 3.3V SLF7028T-100M1R1 10 µF 3.3V SLF7028T-100M1R1 0.1 µF 0.1 µF 10 µF To achieve optimum jitter performance, power supply filtering is required to minimize supply noise modulation of the output clocks. The common sources ...
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IDT82V3285 4 TYPICAL APPLICATION The device supports Master / Slave application, as shown in Figure 15: Line Timing Typical 19.44 MHz and other OC-N clock Typical 19.44 MHz and other OC-N clock SDH/SONET or other Equipment Timing System 155.52 Mbit/s ...
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IDT82V3285 5 MICROPROCESSOR INTERFACE The microprocessor interface provides access to read and write the registers in the device. The microprocessor interface supports the fol- lowing five modes: • EPROM mode; • Multiplexed mode; • Intel mode; • Motorola mode; • ...
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IDT82V3285 5.1 EPROM MODE In this mode, the device is used with an EPROM. The configuration data will be automatically read from the EPROM after the device is pow- ered on. CS A[6:0] AD[7:0] High-Z Table 31: Access Timing Characteristics ...
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IDT82V3285 5.2 MULTIPLEXED MODE ALE AD[7:0] High-Z RDY Table 32: Read Timing Characteristics in Multiplexed Mode Symbol T One cycle time of the master clock out t Valid address to ALE falling edge setup ...
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IDT82V3285 ALE AD[7:0] RDY Table 33: Write Timing Characteristics in Multiplexed Mode Symbol T One cycle time of the master clock out t Valid address to ALE falling edge setup time su1 t Valid ...
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IDT82V3285 5.3 INTEL MODE A[6:0] AD[7:0] RDY Table 34: Read Timing Characteristics in Intel Mode Symbol T One cycle time of the master clock out t Valid address to valid CS setup time su1 ...
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IDT82V3285 A[6:0] AD[7:0] RDY Table 35: Write Timing Characteristics in Intel Mode Symbol T One cycle time of the master clock out t Valid address to valid CS setup time su1 t Valid CS ...
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IDT82V3285 5.4 MOTOROLA MODE CS WR A[6:0] AD[7:0] RDY Table 36: Read Timing Characteristics in Motorola Mode Symbol T One cycle time of the master clock out t Valid address to valid CS setup time su1 t ...
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IDT82V3285 CS WR A[6:0] AD[7:0] RDY Table 37: Write Timing Characteristics in Motorola Mode Symbol T One cycle time of the master clock out t Valid address to valid CS setup time su1 t Valid WR to ...
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IDT82V3285 5.5 SERIAL MODE In a read operation, the active edge of SCLK is selected by CLKE. When CLKE is asserted low, data on SDO will be clocked out on the ris su2 SCLK su1 ...
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IDT82V3285 CS t su2 SCLK su1 SDI R/W A0 SDO Table 39: Write Timing Characteristics in Serial Mode Symbol T One cycle time of the master clock out t Valid SDI to valid SCLK ...
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IDT82V3285 6 JTAG This device is compliant with the IEEE 1149.1 Boundary Scan stan- dard except the following: • The output boundary scan cells do not capture data from the core and the device does not support EXTEST instruction; • ...
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IDT82V3285 7 PROGRAMMING INFORMATION After reset, all the registers are set to their default values. The regis- ters are read or written via the microprocessor interface. Before any write operation, PROTECTION_CNFG is recommended to be confirmed to make sure whether ...
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IDT82V3285 Table 41: Register List and Map (Continued) Address Register Name (Hex) MON_SW_PBO_CNFG - Frequency 0B Monitor, Input Clock Selection & PBO Control MS_SL_CTRL_CNFG - Master Slave 13 Control PROTECTION_CNFG - Register Pro- 7E tection Mode Configuration MPU_SEL_CNFG - Microprocessor ...
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IDT82V3285 Table 41: Register List and Map (Continued) Address Register Name (Hex) IN3_IN4_SEL_PRIORITY_CNFG 28 Input Clock 3 & 4 Priority Configuration * IN5_SEL_PRIORITY_CNFG - Input 2B Clock 5 Priority Configuration * FREQ_MON_FACTOR_CNFG - Fac- 2E tor of Frequency Monitor Configuration ...
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IDT82V3285 Table 41: Register List and Map (Continued) Address Register Name (Hex) IN_FREQ_READ_CH_CNFG - Input 41 Clock Frequency Read Channel Selection IN_FREQ_READ_STS - Input Clock 42 Frequency Read Value IN1_IN2_STS - Input Clock 1 & 2 Sta- 44 tus IN3_IN4_STS ...
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IDT82V3285 Table 41: Register List and Map (Continued) Address Register Name (Hex) T0_DPLL_LOCKED_BW_DAMPING_ 58 CNFG - T0 DPLL Locked Bandwidth & Damping Factor Configuration T0_BW_OVERSHOOT_CNFG - T0 59 DPLL Bandwidth Overshoot Configu- ration PHASE_LOSS_COARSE_LIMIT_CNF Phase Loss Coarse ...
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IDT82V3285 Table 41: Register List and Map (Continued) Address Register Name (Hex) OUT2_FREQ_CNFG - Output Clock 2 6E Frequency Configuration OUT3_FREQ_CNFG - Output Clock 3 6F Frequency Configuration OUT4_FREQ_CNFG - Output Clock 4 70 Frequency Configuration OUT5_FREQ_CNFG - Output Clock ...
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IDT82V3285 ID[15:8] - Device ID 2 Address: 01H Type: Read Default Value: 00010001 7 6 ID15 ID14 Bit Name ID[15:8] The value in the ID[15:0] bits are pre-set, representing the identification number for the IDT82V3285. MPU_PIN_STS - ...
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IDT82V3285 NOMINAL_FREQ[23:16]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 3 Address: 06H Type: Read / Write Default Value: 00000000 7 6 NOMINAL_FRE NOMINAL_FRE Q_VALUE23 Q_VALUE22 Bit Name The NOMINAL_FREQ_VALUE[23:0] bits represent a 2’s complement signed integer. If the value is ...
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IDT82V3285 PHASE_ALARM_TIME_OUT_CNFG - Phase Lock Alarm Time-Out Configuration Address: 08H Type: Read / Write Default Value: 00110010 7 6 MULTI_FACTO MULTI_FACTO TIME_OUT_VA R1 R0 Bit Name MULTI_FACTOR[1: TIME_OUT_VALUE[5:0] Programming Information 5 4 TIME_OUT_VA TIME_OUT_VA ...
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IDT82V3285 INPUT_MODE_CNFG - Input Mode Configuration Address: 09H Type: Read / Write Default Value: 10100XX0 7 6 AUTO_EXT_SY EXT_SYNC_EN NC_EN Bit Name 7 AUTO_EXT_SYNC_EN Refer to the description of the EXT_SYNC_EN bit (b6, 09H). This bit, together with the AUTO_EXT_SYNC_EN ...
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IDT82V3285 DIFFERENTIAL_IN_OUT_OSCI_CNFG - Differential Input / Output Port & Master Clock Configuration Address: 0AH Type: Read / Write Default Value: XXXXX001 Bit Name Reserved. This bit selects a better active edge of ...
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IDT82V3285 MON_SW_PBO_CNFG - Frequency Monitor, Input Clock Selection & PBO Control Address: 0BH Type: Read / Write Default Value: 100X01X1 7 6 FREQ_MON_C LOS_FLAG_TO ULTR_FAST_SW LK _TDO Bit Name The bit selects a reference clock for input clock frequency monitoring. ...
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IDT82V3285 MS_SL_CTRL_CNFG - Master Slave Control Address: 13H Type: Read / Write Default Value: XXXXXXX0 Bit Name Reserved. This bit, together with the MS/SL pin, controls whether the device is configured as ...
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IDT82V3285 MPU_SEL_CNFG - Microprocessor Interface Mode Configuration Address: 7FH Type: Read / Write Default Value: XXXXXXXX Bit Name Reserved. These bits select a microprocessor interface mode: 000: Reserved. 001: ERPOM mode. 010: ...
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IDT82V3285 7.2.2 INTERRUPT REGISTERS INTERRUPT_CNFG - Interrupt Configuration Address: 0CH Type: Read / Write Default Value: XXXXXX10 Bit Name Reserved. This bit determines the output characteristics of the INT_REQ pin. 0: The ...
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IDT82V3285 INTERRUPTS2_STS - Interrupt Status 2 Address: 0EH Type: Read / Write Default Value: 00111111 7 6 T0_OPERATING T0_MAIN_REF_F _MODE AILED Bit Name 7 T0_OPERATING_MODE 6 T0_MAIN_REF_FAILED IN5 Programming Information 5 ...
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IDT82V3285 INTERRUPTS3_STS - Interrupt Status 3 Address: 0FH Type: Read / Write Default Value: 11X10000 7 6 EX_SYNC_ALARM T4_STS Bit Name This bit indicates whether an external sync alarm is raised; i.e., whether there is a transition from ‘0’ to ...
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IDT82V3285 INTERRUPTS2_ENABLE_CNFG - Interrupt Control 2 Address: 11H Type: Read / Write Default Value: 00000000 7 6 T0_OPERATING T0_MAIN_REF_F _MODE AILED Bit Name 7 T0_OPERATING_MODE 6 T0_MAIN_REF_FAILED IN5 INTERRUPTS3_ENABLE_CNFG - Interrupt ...
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IDT82V3285 7.2.3 INPUT CLOCK FREQUENCY & PRIORITY CONFIGURATION REGISTERS IN1_CNFG - Input Clock 1 Configuration Address: 16H Type: Read / Write Default Value: 00000000 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K ...
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IDT82V3285 IN2_CNFG - Input Clock 2 Configuration Address: 17H Type: Read / Write Default Value: 00000000 7 6 DIRECT_DIV LOCK_8K Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 17H). This bit, together with the DIRECT_DIV ...
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IDT82V3285 IN3_IN4_HF_DIV_CNFG - Input Clock 3 & 4 High Frequency Divider Configuration Address: 18H Type: Read / Write Default Value: 00XXXX00 7 6 IN4_DIV1 IN4_DIV0 Bit Name These bits determine whether the HF Divider is used and what the division ...
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IDT82V3285 IN3_CNFG - Input Clock 3 Configuration Address: 19H Type: Read / Write Default Value: 00000011 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 19H). This bit, together with the ...
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IDT82V3285 IN4_CNFG - Input Clock 4 Configuration Address: 1AH Type: Read / Write Default Value: 00000011 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 1AH). This bit, together with the ...
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IDT82V3285 IN5_CNFG - Input Clock 5 Configuration Address: 1FH Type: Read / Write Default Value: 0000XXXX 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 1FH). This bit, together with the ...
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IDT82V3285 PRE_DIV_CH_CNFG - DivN Divider Channel Selection Address: 23H Type: Read / Write Default Value: XXXX0000 Bit Name PRE_DIV_CH_VALUE[3:0] PRE_DIVN[7:0]_CNFG - DivN Divider Division Factor Configuration 1 ...
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IDT82V3285 PRE_DIVN[14:8]_CNFG - DivN Divider Division Factor Configuration 2 Address: 25H Type: Read / Write Default Value: X0000000 7 6 PRE_DIVN_VAL PRE_DIVN_VAL - UE14 Bit Name PRE_DIVN_VALUE[14:8] Programming Information 5 4 PRE_DIVN_VAL PRE_DIVN_VAL UE13 UE12 ...
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IDT82V3285 IN1_IN2_SEL_PRIORITY_CNFG - Input Clock 1 & 2 Priority Configuration * Address: 27H Type: Read / Write Default Value 01010100 / T4 - 00000000 7 6 IN2_SEL_PRIO IN2_SEL_PRIO IN2_SEL_PRIO RITY3 RITY2 Bit Name INn_SEL_PRIORITY[3:0] 3 ...
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IDT82V3285 IN3_IN4_SEL_PRIORITY_CNFG - Input Clock 3 & 4 Priority Configuration * Address: 28H Type: Read / Write Default Value: T0/T4 - 01110110 7 6 IN4_SEL_PRIO IN4_SEL_PRIO RITY3 RITY2 Bit Name INn_SEL_PRIORITY[3: INn_SEL_PRIORITY[3:0] Programming Information ...
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IDT82V3285 IN5_SEL_PRIORITY_CNFG - Input Clock 5 Priority Configuration * Address: 2BH Type: Read / Write Default Value: 11011100 (T0 Master)/11010001 (T0 Slave) 00000000 (T4 Bit Name INn_SEL_PRIORITY[3:0] Programming Information ...
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IDT82V3285 7.2.4 INPUT CLOCK QUALITY MONITORING CONFIGURATION & STATUS REGISTERS FREQ_MON_FACTOR_CNFG - Factor of Frequency Monitor Configuration Address: 2EH Type: Read / Write Default Value: XXXX1011 Bit Name FREQ_MON_FACTOR[3:0] ...
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IDT82V3285 UPPER_THRESHOLD_0_CNFG - Upper Threshold for Leaky Bucket Configuration 0 Address: 31H Type: Read / Write Default Value: 00000110 7 6 UPPER_THRE UPPER_THRE SHOLD_0_DAT SHOLD_0_DAT A7 A6 Bit Name UPPER_THRESHOLD_0_DATA[7:0] LOWER_THRESHOLD_0_CNFG - Lower Threshold for Leaky Bucket ...
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IDT82V3285 DECAY_RATE_0_CNFG - Decay Rate for Leaky Bucket Configuration 0 Address: 34H Type: Read / Write Default Value: XXXXXX01 Bit Name DECAY_RATE_0_DATA[1:0] UPPER_THRESHOLD_1_CNFG - Upper Threshold for Leaky Bucket ...
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IDT82V3285 BUCKET_SIZE_1_CNFG - Bucket Size for Leaky Bucket Configuration 1 Address: 37H Type: Read / Write Default Value: 00001000 7 6 BUCKET_SIZE BUCKET_SIZE BUCKET_SIZE _1_DATA7 _1_DATA6 Bit Name BUCKET_SIZE_1_DATA[7:0] DECAY_RATE_1_CNFG - Decay Rate for Leaky Bucket Configuration ...
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IDT82V3285 LOWER_THRESHOLD_2_CNFG - Lower Threshold for Leaky Bucket Configuration 2 Address: 3AH Type: Read / Write Default Value: 00000100 7 6 LOWER_THRE LOWER_THRE LOWER_THRE SHOLD_2_DAT SHOLD_2_DAT SHOLD_2_DAT A7 A6 Bit Name LOWER_THRESHOLD_2_DATA[7:0] BUCKET_SIZE_2_CNFG - Bucket Size for ...
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IDT82V3285 UPPER_THRESHOLD_3_CNFG - Upper Threshold for Leaky Bucket Configuration 3 Address: 3DH Type: Read / Write Default Value: 00000110 7 6 UPPER_THRE UPPER_THRE UPPER_THRE SHOLD_3_DAT SHOLD_3_DAT SHOLD_3_DAT A7 A6 Bit Name UPPER_THRESHOLD_3_DATA[7:0] LOWER_THRESHOLD_3_CNFG - Lower Threshold for ...
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IDT82V3285 DECAY_RATE_3_CNFG - Decay Rate for Leaky Bucket Configuration 3 Address: 40H Type: Read / Write Default Value: XXXXXX01 Bit Name DECAY_RATE_3_DATA[1:0] IN_FREQ_READ_CH_CNFG - Input Clock Frequency Read Channel ...
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IDT82V3285 IN_FREQ_READ_STS - Input Clock Frequency Read Value Address: 42H Type: Read Default Value: 00000000 7 6 IN_FREQ_VAL IN_FREQ_VAL UE7 UE6 Bit Name These bits represent a 2’s complement signed integer. If the value is multiplied by the value in ...
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IDT82V3285 IN1_IN2_STS - Input Clock 1 & 2 Status Address: 44H Type: Read Default Value: X110X110 7 6 IN2_FREQ_HAR IN2_NO_ACTIVI - D_ALARM TY_ALARM Bit Name IN2_FREQ_HARD_ALARM 5 IN2_NO_ACTIVITY_ALARM 4 IN2_PH_LOCK_ALARM IN1_FREQ_HARD_ALARM 1 IN1_NO_ACTIVITY_ALARM 0 ...
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IDT82V3285 IN3_IN4_STS - Input Clock 3 & 4 Status Address: 45H Type: Read Default Value: X110X110 7 6 IN4_FREQ_HAR IN4_NO_ACTIVI - D_ALARM TY_ALARM Bit Name IN4_FREQ_HARD_ALARM 5 IN4_NO_ACTIVITY_ALARM 4 IN4_PH_LOCK_ALARM IN3_FREQ_HARD_ALARM 1 IN3_NO_ACTIVITY_ALARM 0 ...
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IDT82V3285 IN5_STS - Input Clock 5 Status Address: 48H Type: Read Default Value: X110X110 Bit Name IN5_FREQ_HARD_ALARM 1 IN5_NO_ACTIVITY_ALARM 0 IN5_PH_LOCK_ALARM Programming Information Reserved. This ...
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IDT82V3285 7.2 DPLL INPUT CLOCK SELECTION REGISTERS INPUT_VALID1_STS - Input Clocks Validity 1 Address: 4AH Type: Read Default Value: 00000000 Bit Name Reserved. This bit indicates the validity of ...
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IDT82V3285 REMOTE_INPUT_VALID2_CNFG - Input Clocks Validity Configuration 2 Address: 4DH Type: Read / Write Default Value: XX111111 Bit Name Reserved. This bit controls whether IN5 is allowed to be locked for automatic ...
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IDT82V3285 PRIORITY_TABLE2_STS - Priority Status 2 * Address: 4FH Type: Read Default Value: 00000000 7 6 THIRD_HIGHE THIRD_HIGHE THIRD_HIGHE ST_PRIORITY_ ST_PRIORITY_ ST_PRIORITY_ VALIDATED3 VALIDATED2 Bit Name THIRD_HIGHEST_PRIORITY_VALIDATED[3: SECOND_HIGHEST_PRIORITY_VALIDATED[3:0] Programming Information 5 4 THIRD_HIGHE SECOND_HIGH ...
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IDT82V3285 T0_INPUT_SEL_CNFG - T0 Selected Input Clock Configuration Address: 50H Type: Read / Write Default Value: XXXX0000 Bit Name Reserved. This bit determines T0 input clock selection valid only when ...
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IDT82V3285 T4_INPUT_SEL_CNFG - T4 Selected Input Clock Configuration Address: 51H Type: Read / Write Default Value: X0000000 T4_LOCK_T0 T0_FOR_T4 Bit Name 7 - Reserved. This bit determines whether the T4 DPLL locks DPLL output ...
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IDT82V3285 7.2 DPLL STATE MACHINE CONTROL REGISTERS OPERATING_STS - DPLL Operating Status Address: 52H Type: Read Default Value: 10000001 7 6 EX_SYNC_ALA T4_DPLL_LO T0_DPLL_SOFT RM_MON CK _FREQ_ALARM Bit Name 7 EX_SYNC_ALARM_MON 6 T4_DPLL_LOCK 5 T0_DPLL_SOFT_FREQ_ALARM 4 T4_DPLL_SOFT_FREQ_ALARM ...
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IDT82V3285 T0_OPERATING_MODE_CNFG - T0 DPLL Operating Mode Configuration Address: 53H Type: Read / Write Default Value: XXXXX000 Bit Name T0_OPERATING_MODE[2:0] T4_OPERATING_MODE_CNFG - T4 DPLL Operating Mode Configuration ...
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IDT82V3285 7.2 DPLL & APLL CONFIGURATION REGISTERS T0_DPLL_APLL_PATH_CNFG - T0 DPLL & APLL Path Configuration Address: 55H Type: Read / Write Default Value: 00000X0X 7 6 T0_APLL_PATH T0_APLL_PA T0_APLL_PA 3 TH2 Bit Name T0_APLL_PATH[3:0] ...
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IDT82V3285 T0_DPLL_START_BW_DAMPING_CNFG - T0 DPLL Start Bandwidth & Damping Factor Configuration Address: 56H Type: Read / Write Default Value: 01101111 7 6 T0_DPLL_STA T0_DPLL_STA T0_DPLL_STA RT_DAMPING2 RT_DAMPING1 RT_DAMPING0 Bit Name T0_DPLL_START_DAMPING[2: T0_DPLL_START_BW[4:0] Programming Information ...
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IDT82V3285 T0_DPLL_ACQ_BW_DAMPING_CNFG - T0 DPLL Acquisition Bandwidth & Damping Factor Configuration Address: 57H Type: Read / Write Default Value: 01101111 7 6 T0_DPLL_ACQ T0_DPLL_ACQ T0_DPLL_ACQ _DAMPING2 _DAMPING1 Bit Name T0_DPLL_ACQ_DAMPING[2: T0_DPLL_ACQ_BW[4:0] Programming Information 5 ...
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IDT82V3285 T0_DPLL_LOCKED_BW_DAMPING_CNFG - T0 DPLL Locked Bandwidth & Damping Factor Configuration Address: 58H Type: Read / Write Default Value: 01101011 7 6 T0_DPLL_LOCK T0_DPLL_LOCK T0_DPLL_LOCK ED_DAMPING2 ED_DAMPING1 Bit Name T0_DPLL_LOCKED_DAMPING[2: T0_DPLL_LOCKED_BW[4:0] Programming Information 5 ...
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IDT82V3285 T0_BW_OVERSHOOT_CNFG - T0 DPLL Bandwidth Overshoot Configuration Address: 59H Type: Read / Write Default Value: 1XXX1XXX 7 6 AUTO_BW_SEL - Bit Name This bit determines whether starting or acquisition bandwidth / damping factor is used for T0 DPLL. 0: ...
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IDT82V3285 PHASE_LOSS_COARSE_LIMIT_CNFG - Phase Loss Coarse Detector Limit Configuration * Address: 5AH Type: Read / Write Default Value: 10000101 7 6 COARSE_PH_L WIDE_EN MULTI_PH_APP OS_LIMT_EN Bit Name This bit controls whether the occurrence of the coarse phase loss will result ...
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IDT82V3285 PHASE_LOSS_FINE_LIMIT_CNFG - Phase Loss Fine Detector Limit Configuration * Address: 5BH Type: Read / Write Default Value: 10XXX010 7 6 FINE_PH_LOS_ FAST_LOS_SW LIMT_EN Bit Name 7 FINE_PH_LOS_LIMT_EN 6 FAST_LOS_SW PH_LOS_FINE_LIMT[2:0] Programming Information ...
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IDT82V3285 T0_HOLDOVER_MODE_CNFG - T0 DPLL Holdover Mode Configuration Address: 5CH Type: Read / Write Default Value: 010001XX 7 6 MAN_HOLDOV AUTO_AVG ER Bit Name 7 MAN_HOLDOVER 6 AUTO_AVG 5 FAST_AVG 4 READ_AVG TEMP_HOLDOVER_MODE[1: ...
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IDT82V3285 T0_HOLDOVER_FREQ[15:8]_CNFG - T0 DPLL Holdover Frequency Configuration 2 Address: 5EH Type: Read / Write Default Value: 00000000 7 6 T0_HOLDOVER T0_HOLDOVER T0_HOLDOVER _FREQ15 _FREQ14 Bit Name T0_HOLDOVER_FREQ[15:8] Refer to the description of the T0_HOLDOVER_FREQ[23:16] bits (b7~0, ...
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IDT82V3285 T4_DPLL_APLL_PATH_CNFG - T4 DPLL & APLL Path Configuration Address: 60H Type: Read / Write Default Value: 01000X0X 7 6 T4_APLL_PATH T4_APLL_PA T4_APLL_PA 3 TH2 Bit Name T4_APLL_PATH[3: T4_GSM_GPS_16E1_16T1_SEL[1: T4_12E1_24T1_E3_T3_SEL[1:0] Programming ...
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IDT82V3285 T4_DPLL_LOCKED_BW_DAMPING_CNFG - T4 DPLL Locked Bandwidth & Damping Factor Configuration Address: 61H Type: Read / Write Default Value: 011XXX00 7 6 T4_DPLL_LOCK T4_DPLL_LOCK T4_DPLL_LOCK ED_DAMPING2 ED_DAMPING1 ED_DAMPING0 Bit Name T4_DPLL_LOCKED_DAMPING[2: ...
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IDT82V3285 CURRENT_DPLL_FREQ[23:16]_STS - DPLL Current Frequency Status 3 * Address: 64H Type: Read Default Value: 00000000 7 6 CURRENT_DP CURRENT_DP CURRENT_DP LL_FREQ23 LL_FREQ22 Bit Name CURRENT_DPLL_FREQ[23:16] DPLL_FREQ_SOFT_LIMIT_CNFG - DPLL Soft Limit Configuration Address: 65H Type: Read / ...
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IDT82V3285 DPLL_FREQ_HARD_LIMIT[15:8]_CNFG - DPLL Hard Limit Configuration 2 Address: 67H Type: Read / Write Default Value: 00011001 7 6 DPLL_FREQ_H DPLL_FREQ_H ARD_LIMT15 ARD_LIMT14 Bit Name DPLL_FREQ_HARD_LIMT[15:8] CURRENT_DPLL_PHASE[7:0]_STS - DPLL Current Phase Status 1 * Address: 68H Type: ...
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IDT82V3285 T0_T4_APLL_BW_CNFG - APLL Bandwidth Configuration Address: 6AH Type: Read / Write Default Value: XX01XX01 T0_APLL_BW1 Bit Name Reserved. These bits set the bandwidth for T0 APLL. 00: 100 ...
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IDT82V3285 7.2.8 OUTPUT CONFIGURATION REGISTERS OUT1_FREQ_CNFG - Output Clock 1 Frequency Configuration Address: 6DH Type: Read / Write Default Value: 00001000 7 6 OUT1_PATH_S OUT1_PATH_S OUT1_PATH_S EL3 EL2 Bit Name These bits select an input to OUT1. 0000 ~ 0011: ...
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IDT82V3285 OUT2_FREQ_CNFG - Output Clock 2 Frequency Configuration Address: 6EH Type: Read / Write Default Value: 00000110 7 6 OUT2_PATH_S OUT2_PATH_S OUT2_PATH_S EL3 EL2 Bit Name These bits select an input to OUT2. 0000 ~ 0011: The output of T0 ...
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IDT82V3285 OUT3_FREQ_CNFG - Output Clock 3 Frequency Configuration Address: 6FH Type: Read / Write Default Value: 00000100 7 6 OUT3_PATH_S OUT3_PATH_S OUT3_PATH_S EL3 EL2 Bit Name These bits select an input to OUT3. 0000 ~ 0011: The output of T0 ...
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IDT82V3285 OUT4_FREQ_CNFG - Output Clock 4 Frequency Configuration Address:70H Type: Read / Write Default Value: 00000110 7 6 OUT4_PATH_S OUT4_PATH_S OUT4_PATH_S EL3 EL2 Bit Name These bits select an input to OUT4. 0000 ~ 0011: The output of T0 APLL. ...
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IDT82V3285 OUT5_FREQ_CNFG - Output Clock 5 Frequency Configuration Address:71H Type: Read / Write Default Value: 00001000 7 6 OUT5_PATH_S OUT5_PATH_S OUT5_PATH_S EL3 EL2 Bit Name These bits select an input to OUT5. 0000 ~ 0011: The output of T0 APLL. ...
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IDT82V3285 OUTPUT_INV1 - Output Clock Invert Configuration Address:73H Type: Read / Write Default Value: 01000000 Bit Name Reserved. This bit determines whether the output on OUT3 is inverted. 4 ...
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IDT82V3285 FR_MFR_SYNC_CNFG - Frame Sync & Multiframe Sync Output Configuration Address:74H Type: Read / Write Default Value: 01100000 7 6 IN_2K_4K_8K_I 8K_EN NV Bit Name 7 IN_2K_4K_8K_INV 6 8K_EN 5 2K_EN 4 2K_8K_PUL_POSITION 3 8K_INV 2 8K_PUL 1 2K_INV 0 ...
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IDT82V3285 7.2.9 PBO & PHASE OFFSET CONTROL REGISTERS PHASE_MON_PBO_CNFG - Phase Transient Monitor & PBO Configuration Address:78H Type: Read / Write Default Value: 0X000110 7 6 IN_NOISE_WIN - DOW Bit Name 7 IN_NOISE_WINDOW PH_MON_EN 4 PH_MON_PBO_EN 3 ...
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IDT82V3285 PHASE_OFFSET[9:8]_CNFG - Phase Offset Configuration 2 Address:7BH Type: Read / Write Default Value: 0XXXXX00 7 6 PH_OFFSET_E - N Bit Name This bit determines whether the input-to-output phase offset is enabled. If the device is configured as the Master, ...
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IDT82V3285 7.2.10 SYNCHRONIZATION CONFIGURATION REGISTERS SYNC_MONITOR_CNFG - Sync Monitor Configuration Address:7CH Type: Read / Write Default Value: X0101011 SYNC_MON_LIMT2 Bit Name 7 - Reserved. These bits set the limit for the external sync alarm. 000: ±1 UI. ...
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IDT82V3285 8 THERMAL MANAGEMENT The device operates over the industry temperature range -40°C ~ +85°C. To ensure the functionality and reliability of the device, the maxi- mum junction temperature T should not exceed 125°C. In some jmax applications, the device ...
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IDT82V3285 9 ELECTRICAL SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATING Table 44: Absolute Maximum Rating Symbol OUT T Ambient Operating Temperature Range A T STOR 9.2 RECOMMENDED OPERATION CONDITIONS Table 45: Recommended Operation Conditions Symbol V Power ...
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IDT82V3285 9.3 I/O SPECIFICATIONS 9.3.1 CMOS INPUT / OUTPUT PORT From Table 46 to Table 49 3 Table 46: CMOS Input Port Electrical Characteristics Parameter Description V Input Voltage High IH V Input Voltage Low IL ...
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IDT82V3285 9.3.2 PECL / LVDS INPUT / OUTPUT PORT 9.3.2.1 PECL Input / Output Port 130 Ω 50 Ω (transmission line) 82 Ω 2 kHz to 667 MHz 130 Ω ...
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IDT82V3285 Table 50: PECL Input / Output Port Electrical Characteristics Parameter Description V Input Low Voltage, Differential Inputs IL V Input High Voltage, Differential Inputs IH V Input Differential Voltage ID V Input Low Voltage, Single-ended Input IL_S V Input ...
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IDT82V3285 9.3.2.2 LVDS Input / Output Port 50 Ω (transmission line) 2 kHz 100 Ω to 667 MHz 50 Ω (transmission line) 50 Ω (transmission line) 2 kHz to 100 Ω 667 MHz 50 Ω (transmission line) Figure 29. Recommended ...
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IDT82V3285 9.4 JITTER & WANDER PERFORMANCE Table 52: Output Clock Jitter Generation 1 Test Definition N x 2.048MHz without APLL N x 2.048MHz with T0/T4 APLL N x 1.544 MHz without APLL N x 1.544 MHz with T0/T4 APLL 44.736 ...
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IDT82V3285 Table 53: Output Clock Phase Noise 1 Output Clock 622.08 MHz (T0 DPLL + T0/T4 APLL) 155.52 MHz (T0 DPLL + T0/T4 APLL) 38.88 MHz (T0 DPLL + T0/T4 APLL) 16E1 (T0/T4 APLL) 16T1 (T0/T4 APLL) E3 (T0/T4 APLL) ...
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IDT82V3285 Table 58: T0 DPLL Jitter Transfer & Damping Factor 3 dB Bandwidth Programmable Damping Factor 0.5 mHz 1 mHz 2 mHz 4 mHz 8 mHz 15 mHz 30 mHz 60 mHz 0.1 Hz 0.3 Hz 0.6 Hz 1.2 Hz ...
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IDT82V3285 9.5 OUTPUT WANDER GENERATION template tested result Electrical Specifications Figure 31. Output Wander Generation 136 WAN PLL template tested result April 11, 2007 ...
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IDT82V3285 9.6 INPUT / OUTPUT CLOCK TIMING The inputs and outputs are aligned ideally. But due to the circuit delays, there is delay between the inputs and outputs. 8 kHz Input Clock 8 kHz Output Clock 6.48 MHz Input Clock ...
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IDT82V3285 9.7 OUTPUT CLOCK TIMING Table 61: Output Clock Timing Symbol Electrical Specifications MFRSYNC_2K/ ...
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ADSL --- APLL --- ATM --- BITS --- CMOS --- DCO --- DPLL --- DSL --- DSLAM --- DWDM --- EPROM --- GPS --- GSM --- IIR --- IP --- ISDN --- JTAG --- LPF --- LVDS --- ...
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IDT82V3285 PECL --- PFD --- PLL --- RMS --- PRS --- SDH --- SEC --- SMC --- SONET --- SSU --- STM --- TCM-ISDN --- TDEV --- UI --- WLL --- Glossary Positive Emitter Coupled Logic Phase & Frequency Detector ...
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A Averaged Phase Error ........................................................................ 32 B Bandwidths and Damping Factors ..................................................... 32 Acquisition Bandwidth and Damping Factor ............................... 32 Locked Bandwidth and Damping Factor ..................................... 32 Starting Bandwidth and Damping Factor .................................... 32 C Calibration .......................................................................................... 18 Coarse Phase ...
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IDT82V3285 PFD .................................................................................................... 32 Phase Lock Alarm ....................................................................... 26 Phase Offset ....................................................................................... 35 Phase-compared ......................................................................... 25 Phase-time ......................................................................................... 35 Pre-Divider ......................................................................................... 20 DivN Divider ................................................................................ 20 HF Divider ................................................................................... 20 Lock 8k Divider ........................................................................... 20 Index Reference ...
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IDT82V3285 ORDERING INFORMATION XXXXXXX IDT XX Device Type DATASHEET DOCUMENT HISTORY CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 www.idt.com IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. X Process/ Temperature Range Blank ...