IDT82V3285DQ IDT, Integrated Device Technology Inc, IDT82V3285DQ Datasheet - Page 41

• Manufacturer Part Number: IDT82V3285DQ
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3285DQ

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.14
device.
configured as the Slave. The configuration is made by the MS/SL pin
and the MS_SL_CTRL bit (b0, 13H), as shown in
Table 28: Device Master / Slave Control
Functional Description
IDT82V3285
Master / Slave configuration is only supported by the T0 path of the
Two devices should be used together in order to:
Of the two devices, one is configured as the Master and the other is
• Enable system protection against single chip failure;
• Guarantee no service interrupt during system maintenance, such
MS/SL pin
as software or hardware upgrade.
High
Low
Master / Slave Control
MASTER / SLAVE CONFIGURATION
Backplane
Hardware
control
MS_SL_CTRL Bit
0
1
0
1
Figure 13. Physical Connection Between Two Devices
Table
Result
Master
Master
28:
Slave
Slave
EX_SYNC1
EX_SYNC1
MS/SL
MS/SL
IN1
IN2
IN3
IN4
IN5
IN1
IN2
IN3
IN4
IN5
Chip A
Chip B
MFRSYNC_2K
MFRSYNC_2K
FRSYNC_8K/
FRSYNC_8K/
41
input clock and the frame sync output signals from the two devices are
at the same frequency offset and phase. Refer to
SYNC Output Signals
the IN5 should not be selected by the T0 DPLL; in the Slave, the follow-
ing functions are automatically forced:
tions can still be configured, but their configuration does not take any
effect. The frequency of the T0 selected input clock IN5 is recommended
to be 6.48 MHz.
OUT1
OUT5
OUT1
OUT5
In this application, all the output clocks derived from the T0 selected
The difference between the Master and the Slave is: in the Master,
In the Slave, the corresponding registers of the above forced func-
.
.
.
.
.
.
• The T0 selected input clock is IN5;
• T0 PBO is disabled;
• T0 DPLL operates at the acquisition bandwidth and damping fac-
• EX_SYNC1 is used for synchronization;
• T0 DPLL operates in Locked mode.
tor;
one output
frame sync
frame sync
one output
one output
one output
clock
signal
signal
clock
for details.
Backplane connections
Backplane
Chapter 3.13.2 Frame
April 11, 2007
WAN PLL