IDT82V3285DQ IDT, Integrated Device Technology Inc, IDT82V3285DQ Datasheet - Page 121

• Manufacturer Part Number: IDT82V3285DQ
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3285DQ

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

OUT5_FREQ_CNFG - Output Clock 5 Frequency Configuration
Programming Information
IDT82V3285
Address:71H
Type: Read / Write
Default Value: 00001000
OUTPUT_INV2 - Output Clock 4 & 5 Invert Configuration
Address:72H
Type: Read / Write
Default Value: 01000000
OUT5_PATH_S
7 - 4
3 - 0
7 - 2
Bit
Bit
1
0
EL3
7
7
-
OUT5_PATH_SEL[3:0]
OUT5_DIVIDER[3:0]
OUT5_INV
OUT4_INV
OUT5_PATH_S
Name
Name
-
EL2
6
6
-
Reserved.
This bit determines whether the output on OUT5 is inverted.
0: Not inverted. (default)
1: Inverted.
This bit determines whether the output on OUT4 is inverted.
0: Not inverted. (default)
1: Inverted.
These bits select an input to OUT5.
0000 ~ 0011: The output of T0 APLL. (default: 0000)
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
1000 ~ 1011: The output of T4 APLL.
1100: The output of T4 DPLL 77.76 MHz path.
1101: The output of T4 DPLL 12E1/24T1/E3/T3 path.
1110: The output of T4 DPLL 16E1/16T1 path.
1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path.
These bits select a division factor of the divider for OUT5.
The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output
(selected by the OUT5_PATH_SEL[3:0] bits (b7~4, 71H)). If the signal is derived from one of the T0/T4 DPLL outputs,
please refer to
Table 25
OUT5_PATH_S
EL1
5
5
-
for the division factor selection.
Table 24
OUT5_PATH_S
for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to
EL0
4
4
-
121
OUT5_DIVIDER
3
3
3
-
Description
Description
OUT5_DIVIDER
2
2
2
-
OUT5_DIVIDER
OUT5_INV
1
1
1
OUT5_DIVIDER
OUT4_INV
April 11, 2007
0
0
0
WAN PLL