IDT82V3285DQ IDT, Integrated Device Technology Inc, IDT82V3285DQ Datasheet - Page 6

• Manufacturer Part Number: IDT82V3285DQ
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3285DQ

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

List of Tables
Table 1: Pin Description ............................................................................................................................................................................................. 13
Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 18
Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 19
Table 4: Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 20
Table 5: Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 22
Table 6: Input Clock Selection for T0 Path ................................................................................................................................................................ 23
Table 7: Input Clock Selection for T4 Path ................................................................................................................................................................ 23
Table 8: External Fast Selection ................................................................................................................................................................................ 23
Table 9: Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 24
Table 10: Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 25
Table 11: Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 25
Table 12: Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 26
Table 13: Conditions of Qualified Input Clocks Available for T0 & T4 Selection ......................................................................................................... 27
Table 14: Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 28
Table 15: T0 DPLL Operating Mode Control ............................................................................................................................................................... 29
Table 16: T4 DPLL Operating Mode Control ............................................................................................................................................................... 31
Table 17: Related Bit / Register in Chapter 3.9 ........................................................................................................................................................... 31
Table 18: Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 32
Table 19: Frequency Offset Control in Holdover Mode ............................................................................................................................................... 33
Table 20: Holdover Frequency Offset Read ................................................................................................................................................................ 33
Table 21: Related Bit / Register in Chapter 3.10 ......................................................................................................................................................... 34
Table 22: Related Bit / Register in Chapter 3.11 ......................................................................................................................................................... 36
Table 23: Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 37
Table 24: Outputs on OUT1 ~ OUT5 if Derived from T0/T4 DPLL Outputs ................................................................................................................ 37
Table 25: Outputs on OUT1 ~ OUT5 if Derived from T0/T4 APLL .............................................................................................................................. 38
Table 26: Synchronization Control ............................................................................................................................................................................... 39
Table 27: Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 40
Table 28: Device Master / Slave Control ..................................................................................................................................................................... 41
Table 29: Related Bit / Register in Chapter 3.15 ......................................................................................................................................................... 42
Table 30: Microprocessor Interface ............................................................................................................................................................................. 45
Table 31: Access Timing Characteristics in EPROM Mode ......................................................................................................................................... 46
Table 32: Read Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 47
Table 33: Write Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 48
Table 34: Read Timing Characteristics in Intel Mode .................................................................................................................................................. 49
Table 35: Write Timing Characteristics in Intel Mode .................................................................................................................................................. 50
Table 36: Read Timing Characteristics in Motorola Mode ........................................................................................................................................... 51
Table 37: Write Timing Characteristics in Motorola Mode ........................................................................................................................................... 52
Table 38: Read Timing Characteristics in Serial Mode ................................................................................................................................................ 53
Table 39: Write Timing Characteristics in Serial Mode ................................................................................................................................................ 54
Table 40: JTAG Timing Characteristics ....................................................................................................................................................................... 55
Table 41: Register List and Map .................................................................................................................................................................................. 56
Table 42: Power Consumption and Maximum Junction Temperature ....................................................................................................................... 127
Table 43: Thermal Data ............................................................................................................................................................................................. 127
Table 44: Absolute Maximum Rating ......................................................................................................................................................................... 128
Table 45: Recommended Operation Conditions ........................................................................................................................................................ 128
Table 46: CMOS Input Port Electrical Characteristics ............................................................................................................................................... 129
Table 47: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ 129
Table 48: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... 129
List of Tables
6
April 11, 2007