IDT82V3285DQ IDT, Integrated Device Technology Inc, IDT82V3285DQ Datasheet - Page 4

• Manufacturer Part Number: IDT82V3285DQ
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3285DQ

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Table of Contents
4 TYPICAL APPLICATION ................................................................................................................................................. 44
5 MICROPROCESSOR INTERFACE .................................................................................................................................. 45
6 JTAG ................................................................................................................................................................................ 55
7 PROGRAMMING INFORMATION .................................................................................................................................... 56
8 THERMAL MANAGEMENT ........................................................................................................................................... 127
IDT82V3285
3.11 T0 / T4 DPLL OUTPUT ................................................................................................................................................................................. 35
3.12 T0 / T4 APLL ................................................................................................................................................................................................. 37
3.13 OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 37
3.14 MASTER / SLAVE CONFIGURATION ......................................................................................................................................................... 41
3.15 INTERRUPT SUMMARY ............................................................................................................................................................................... 42
3.16 T0 AND T4 SUMMARY ................................................................................................................................................................................. 42
3.17 POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 43
4.1 MASTER / SLAVE APPLICATION ............................................................................................................................................................... 44
5.1 EPROM MODE .............................................................................................................................................................................................. 46
5.2 MULTIPLEXED MODE .................................................................................................................................................................................. 47
5.3 INTEL MODE ................................................................................................................................................................................................. 49
5.4 MOTOROLA MODE ...................................................................................................................................................................................... 51
5.5 SERIAL MODE .............................................................................................................................................................................................. 53
7.1 REGISTER MAP ............................................................................................................................................................................................ 56
7.2 REGISTER DESCRIPTION ........................................................................................................................................................................... 61
8.1 JUNCTION TEMPERATURE ...................................................................................................................................................................... 127
8.2 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 127
3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 33
3.11.1 PFD Output Limit ............................................................................................................................................................................ 35
3.11.2 Frequency Offset Limit .................................................................................................................................................................. 35
3.11.3 PBO (T0 only) ................................................................................................................................................................................. 35
3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 35
3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 35
3.13.1 Output Clocks ................................................................................................................................................................................. 37
3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 39
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10 Synchronization Configuration Registers ................................................................................................................................. 126
3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 32
3.10.1.5 Holdover Mode ................................................................................................................................................................. 32
3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 33
3.10.2.1 Free-Run Mode ................................................................................................................................................................ 33
3.10.2.2 Locked Mode .................................................................................................................................................................... 33
3.10.2.3 Holdover Mode ................................................................................................................................................................. 33
3.11.5.1 T0 Path ............................................................................................................................................................................. 35
3.11.5.2 T4 Path ............................................................................................................................................................................. 36
Global Control Registers ............................................................................................................................................................... 61
Interrupt Registers ......................................................................................................................................................................... 70
Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 74
Input Clock Quality Monitoring Configuration & Status Registers ........................................................................................... 85
T0 / T4 DPLL Input Clock Selection Registers ............................................................................................................................. 96
T0 / T4 DPLL State Machine Control Registers ......................................................................................................................... 101
T0 / T4 DPLL & APLL Configuration Registers .......................................................................................................................... 103
Output Configuration Registers .................................................................................................................................................. 117
PBO & Phase Offset Control Registers ...................................................................................................................................... 124
3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 33
3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 33
3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 33
3.10.1.5.4 Manual ........................................................................................................................................................... 33
3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 33
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April 11, 2007
WAN PLL