PSB21373HV11XT Infineon Technologies, PSB21373HV11XT Datasheet - Page 88

• Manufacturer Part Number: PSB21373HV11XT
• Manufacturer: Infineon Technologies
• Type: PCMr

Specifications of PSB21373HV11XT

• Number Of Channels: 1
• Number Of Adc's: 1
• Number Of Dac's: 1
• Number Of Adc Inputs: 1
• Pin Count: 44
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

The following description of the receive FIFO operation is illustrated in figure 46 for a
RFIFO block size (threshold) of 16 and 32 bytes.
The RFIFO requests service from the microcontroller by setting a bit in the ISTAH
register, which causes an interrupt (RPF, RME, RFO). The microcontroller then reads
status information (RBCH,RBCL), data from the RFIFO and changes the RFIFO block
size (EXMR.RFBS). A block transfer is completed by the microcontroller via a receive
message complete (CMDR.RMC) command. This causes the space of the transferred
bytes being released for new data and in case the frame was complete (RME) the reset
of the receive byte counter RBC (RBCH,RBCL).
The total length of the frame is contained in the RBCH and RBCL registers (RBC11...0).
If a frame is longer than 4095 bytes, the RBCH.OV (overflow) bit will be set. The least
significant bits of RBCL contain the number of valid bytes in the last data block indicated
by RME (length of last data block
contain the number of bytes in the last data block or number of complete data blocks
respectively. If the number of bytes in the last data block is ’0’ the length of the last
received block is equal to the block size.
Table 7
Receive Byte Count with RBC11...0 in the RBCH and RBCL registers
’00’
’01’
’10’
’11’
The transfer block size (EXMR.RFBS) is 32 bytes by default. If it is necessary to react to
an incoming frame within the first few bytes the microcontroller can set the RFIFO block
size to a smaller value. Each time a CMDR.RMC or CMDR.RRES command is issued,
the RFIFO access controller sets its block size to the value specified in EXMR.RFBS, so
the microcontroller has to write the new value for RFBS before the RMC command.
When setting an initial value for RFBS before the first HDLC activities, a RRES
command must be issued afterwards.
The RFIFO can hold any number of frames fitting in the 64 bytes. At the end of a frame,
the RSTA byte is always appended.
All generated interrupts are inserted together with all additional information into a wait
line to be individually passed to the host. For example if several data blocks have been
received to be read by the host and the host acknowledges the current block, a new RPF
or RME interrupt from the wait line is immediately generated to indicate new data.
Data Sheet
EXMR.RFBS
bits
Selected
block size
32 byte
16 byte
8 byte
4 byte
complete
data blocks in
RBC11...5
RBC11...4
RBC11...3
RBC11...2
selected block size). Table 7 shows which RBC bits
88
Number of
bytes in the last
data block in
RBC4...0
RBC3...0
RBC2...0
RBC1...0
PSB 21373
2002-05-13