AD9643BCPZ-210 Analog Devices Inc, AD9643BCPZ-210 Datasheet - Page 12

• Manufacturer Part Number: AD9643BCPZ-210
• Description: IC ADC 14BIT SRL 210MSPS 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9643BCPZ-210

• Sampling Rate: 210MSPS
• Input Channel Type: Differential, Single Ended
• Data Interface: 3-Wire, Serial
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Rohs Compliant: Yes
• Resolution (bits): 14bit
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

AD9643
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions for Interleaved Parallel LVDS Mode
Pin No.
ADC Power Supplies
ADC Analog
Digital Input
Digital Outputs
10, 19, 28, 37
49, 50, 53, 54, 59, 60, 63, 64
4, 5, 6, 7, 55, 56, 58
0
51
52
62
61
57
1
2
3
9
8
12
11
14
13
16
15
18
Mnemonic
DRVDD
AVDD
AGND,
Exposed Paddle
VIN+A
VIN−A
VIN+B
VIN−B
VCM
CLK+
CLK−
SYNC
D0+ (LSB)
D0− (LSB)
D1+
D1−
D2+
D2−
D3+
D3−
D4+
DNC
INDICATOR
(LSB) D0–
(LSB) D0+
DRVDD
Figure 4. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
SYNC
CLK+
CLK–
PIN 1
DNC
DNC
DNC
DNC
D1–
D1+
D2–
D2+
D3–
D3+
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE
PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART.
THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND
FOR PROPER OPERATION.
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
Type
Supply
Supply
Ground
Input
Input
Input
Input
Output
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Rev. A | Page 12 of 36
PARALLEL LVDS
(Not to Scale)
TOP VIEW
AD9643
Description
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Do Not Connect. Do not connect to this pin.
Analog Ground. The exposed thermal paddle on the bottom of the
package provides the analog ground for the part. This exposed
paddle must be connected to ground for proper operation.
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Common-Mode Level Bias Output for Analog Inputs. This pin
should be decoupled to ground using a 0.1 μF capacitor.
ADC Clock Input—True.
ADC Clock Input—Complement.
Digital Synchronization Pin. Slave mode only.
Channel A/Channel B LVDS Output Data 0—True.
Channel A/Channel B LVDS Output Data 0—Complement.
Channel A/Channel B LVDS Output Data 1—True.
Channel A/Channel B LVDS Output Data 1—Complement.
Channel A/Channel B LVDS Output Data 2—True.
Channel A/Channel B LVDS Output Data 2—Complement.
Channel A/Channel B LVDS Output Data 3—True.
Channel A/Channel B LVDS Output Data 3—Complement.
Channel A/Channel B LVDS Output Data 4—True.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDWN
OEB
CSB
SCLK
SDIO
OR+
OR–
D13+ (MSB)
D13– (MSB)
D12+
D12–
DRVDD
D11+
D11–
D10+
D10–