AD9643BCPZ-210 Analog Devices Inc, AD9643BCPZ-210 Datasheet - Page 34

• Manufacturer Part Number: AD9643BCPZ-210
• Description: IC ADC 14BIT SRL 210MSPS 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9643BCPZ-210

• Sampling Rate: 210MSPS
• Input Channel Type: Differential, Single Ended
• Data Interface: 3-Wire, Serial
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Rohs Compliant: Yes
• Resolution (bits): 14bit
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

AD9643
Addr
(Hex)
0x1F
0x20
0x24
0x25
0x3A
0x59
1
MEMORY MAP REGISTER DESCRIPTION
For more information on functions controlled in Register 0x00
to Register 0x25, see the
to High Speed ADCs via SPI.
Sync Control (Register 0x3A)
Bits[7:3]—Reserved
Bit 2—Clock Divider Next Sync Only
If the master sync buffer enable bit (Address 0x3A, Bit 0) and
the clock divider sync enable bit (Address 0x3A, Bit 1) are high,
Bit 2 allows the clock divider to sync to the first sync pulse that
it receives and to ignore the rest. The clock divider sync enable
bit (Address 0x3A, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
enabled when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
The channel index register at Address 0x05 should be set to 0x03 (default) when writing to Address 0x00.
Register
Name
User Test
Pattern 4 LSB
(global)
User Test
Pattern 4 MSB
(global)
BIST signature
LSB (local)
BIST signature
MSB (local)
Sync control
(global)
SYNC pin
control
(local)
Bit 7
(MSB)
Open
Open
AN-877 Application
Bit 6
Open
Open
Note, Interfacing
Bit 5
Open
Open
Bit 4
Open
Open
User Test Pattern 4[15:8]
User Test Pattern 4[7:0]
Rev. A | Page 34 of 36
BIST signature[15:8]
BIST signature[7:0]
Bit 3
Open
Open
Bit 0—Master Sync Buffer Enable
Bit 0 must be set high to enable any of the sync functions. If the
sync capability is not used, this bit should remain low to
conserve power.
SYNC Pin Control (Register 0x59)
Bits [7:2]—Reserved
Bit 1—SYNC Pin Sensitivity
If Bit 1 is set to 0, the SYNC input responds to a level. If this bit
is set low, the SYNC input responds to the edge (rising or
falling) set in Bit 0 of Address 0x59.
Bit 0—SYNC Pin Edge Sensitivity
If Bit 1 is set high, setting Bit 0 to a 0 causes the SYNC input to
respond to a falling edge. If this bit is set, the SYNC input
respond to a rising edge.
Bit 2
Clock
divider
next sync
only
Open
Bit 1
Clock
divider
sync
enable
SYNC pin
sensitivity
0 = sync
on high
level
1 = sync
on edge
Bit 0
(LSB)
SYNC pin
edge
sensitivity
0 = sync on
falling edge
1 = sync on
rising edge
Master sync
buffer enable
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x00
0x00
Default
Notes/
Comments
Read only.
Read only.