MK2069-01GITR IDT, Integrated Device Technology Inc, MK2069-01GITR Datasheet - Page 3

• Manufacturer Part Number: MK2069-01GITR
• Description: IC VCXO CLK SYNCHRONIZER 56TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Synchronizerr

Specifications of MK2069-01GITR

• Pll: Yes
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:3
• Differential - Input:output: No/No
• Frequency - Max: 160MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 160MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Descriptions
IDT® VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
MK2069-01
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
Number
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
1
2
3
4
5
6
7
8
9
Name
GNDT
GNDV
GNDP
VDDT
VDDV
ICLK2
ICLK0
RCLK
FV10
FV11
ISET
GND
MX1
CLR
LDC
LDR
RV0
LFR
Pin
ST0
ST1
RT0
RT1
FT0
FT1
FT2
FT3
FT4
FT5
FV0
FV1
FV2
FV3
FV4
FV5
FV6
FV7
FV8
FV9
X1
X2
LF
Ground
Ground
Ground
Ground
Output
Power
Power
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Pin
-
-
-
-
-
-
-
Scaling Divider bit 0 input, Translator PLL (internal pull-up).
Scaling Divider bit 1 input, Translator PLL (internal pull-up).
Reference Divider bit 0 input, Translator PLL (internal pull-up).
Reference Divider bit 1 input, Translator PLL (internal pull-up).
Feedback Divider bit 0 input, Translator PLL (internal pull-up).
Feedback Divider bit 1 input, Translator PLL (internal pull-up).
Feedback Divider bit 2 input, Translator PLL (internal pull-up).
Feedback Divider bit 3 input, Translator PLL (internal pull-up).
Feedback Divider bit 4 input, Translator PLL (internal pull-up).
Feedback Divider bit 5 input, Translator PLL (internal pull-up).
Reference Divider bit 0 input, VCXO PLL (internal pull-up).
Power Supply connection for translator PLL.
Ground connection for translator PLL.
Crystal oscillator input. Connect this pin to the external reference crystal.
Power Supply connection for VCXO PLL.
Crystal oscillator output. Connect this pin to the external reference crystal.
Ground connection for VCXO PLL.
Loop filter connection, reference node. Refer to loop filter circuit on page 6.
Loop filter connection, active node. Refer to loop filter circuit on page 6.
Charge pump current setting input. Refer to loop filter circuit on page 6.
Feedback Divider bit 0 input, VCXO PLL (internal pull-up).
Feedback Divider bit 1 input, VCXO PLL (internal pull-up).
Feedback Divider bit 2 input, VCXO PLL (internal pull-up).
Feedback Divider bit 3 input, VCXO PLL (internal pull-up).
Feedback Divider bit 4 input, VCXO PLL (internal pull-up).
Feedback Divider bit 5 input, VCXO PLL (internal pull-up).
Feedback Divider bit 6 input, VCXO PLL (internal pull-up).
Feedback Divider bit 7 input, VCXO PLL (internal pull-up).
Feedback Divider bit 8 input, VCXO PLL (internal pull-up).
Feedback Divider bit 9 input, VCXO PLL (internal pull-up).
Feedback Divider bit 10 input, VCXO PLL (internal pull-up).
Feedback Divider bit 11 input, VCXO PLL (internal pull-up).
Input MUX selection bit 1 (internal pull-up).
Reference clock input 2.
Reference clock input 0. 5V tolerant input.
Clear input, clears VCXO PLL dividers when low (internal pull-up).
Lock detector threshold setting circuit connection. Refer to circuit on page 10.
Digital ground connection.
Lock detector threshold setting circuit connection. Refer to circuit on page 10.
VCXO PLL phase detector Reference Clock output.
Ground connection for output drivers (VCLK, TCLK, RCLK, LD, LDR).
3
Pin Description
VCXO AND SYNTHESIZER
MK2069-01
REV K 051310