MK2069-01GITR IDT, Integrated Device Technology Inc, MK2069-01GITR Datasheet - Page 9

• Manufacturer Part Number: MK2069-01GITR
• Description: IC VCXO CLK SYNCHRONIZER 56TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Synchronizerr

Specifications of MK2069-01GITR

• Pll: Yes
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:3
• Differential - Input:output: No/No
• Frequency - Max: 160MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 160MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Notes on Setting the RV, FV and SV Divider
As shown in the loop bandwidth and damping factor
equations on page 6, or by using the filter response software
available from IDT, increasing FV or SV decreases both
bandwidth and damping factor. Many applications require
that SV = 1. In these cases, one way to decrease loop
bandwidth is to increase the value of FV, which is
accompanied by an increase in the value of RV to maintain
Example Loop Filter Component Value
Loop Filter Capacitor Type
Loop filters must use specific types of capacitors.
Recommendations for these capacitors can be found at
www.idt.com/?app=calculators&source=support_menu.
Input MUX
The MK2069-01 incorporates an input clock multiplexer or
‘mux’ that allows selection between one of three alternate
reference inputs supplied to the device. The mux input
IDT® VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
19.44 MHz
MK2069-01
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
Clock
8 kHz
8 kHz
8 kHz
Input
Notes:
1) This filter configuration assures a passband ripple compliant with Bellcore GR-1244 to satisfy wander transfer
requirements (<0.2 dB ripple is required) of a network node. It can be used following a system synchronizer such as
the MT9045 to provide clock jitter attenuation while maintaining Stratum 3 compliance. A 155.52 MHz TCLK output
generated with the VCXO PLL configuration will be OC-3 and OC-12 timing jitter compliant.
2) This is a reduced cost and size variant of the above filter, due to the decreased size of C
compliance is not needed, such as in a network access application.
3) This configuration is used to generate a DS3 clock of 44.768 MHz at the TCLK output. This configuration is GR-1244
compliant.
4) The MK2069-02 or MK2069-04 may be more suitable for this application since the VCXO feedback divider can be
increased (>128), enabling a lower bandwidth for improved jitter attenuation.
Values
22.368
(MHz)
19.44
19.44
19.44
Freq
Xtal
22.368
VCLK
(MHz)
19.44
19.44
19.44
128
Div
RV
1
1
1
2430
2430
2796
128
Div
FV
Div
SV
1
1
1
1
1 M
1 M
1 M
1 M
R
SET
560 k
560 k
680 k
27 k
R
S
9
0.1 F 4.7 nF 27 Hz
1 F
1 F
1 F
the same PLL frequency multiplication ratio.
However, the phase detector frequency, F
be considered. F
by the value of the RV divider. F
least 20x the loop bandwidth to prevent loop modulation
(phase noise) by the phase detector frequency. The phase
detector jitter tolerance limit (use 0.4UI) and input phase
noise frequency aliasing should be considerations as well.
selection pins are asynchronous and non-latched. Please
refer to the Input MUX Selection Table on page 2. Note that
inputs ICLK0 and ICLK1 are 5V tolerant, whereas ICLK2 is
not.
Input Phase Compensation Circuit
The VCXO PLL includes a special input clock phase
compensation circuit. It is used when selecting a new
reference input that has a clock phase differing from the
C
S
4.7 nF 22 Hz
4.7 nF 20 Hz
47 nF
C
P
(-3dB)
25 Hz
Loop
BW
PD
is equal to the input frequency divided
Damp.
Loop
0.85
4.0
1.4
4.5
0.15dB at 1Hz
0.12dB at 1Hz
1.2dB at 6Hz
1.8dB at 8Hz
Passband
S
Peaking
VCXO AND SYNTHESIZER
PD
. It is useful when GR-1244
should be typically at
MK2069-01
PD
, also needs to
Note
1
2
3
4
REV K 051310