MK2069-01GITR IDT, Integrated Device Technology Inc, MK2069-01GITR Datasheet - Page 6

• Manufacturer Part Number: MK2069-01GITR
• Description: IC VCXO CLK SYNCHRONIZER 56TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Synchronizerr

Specifications of MK2069-01GITR

• Pll: Yes
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:3
• Differential - Input:output: No/No
• Frequency - Max: 160MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 160MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Setting TCLK Output Frequency
The clock frequency of TCLK is determined by:
The frequency range of TCLK is set by the operational range
of the internal VCO circuit and the output divider selections:
A higher VCO frequency will generally produce lower phase
noise and therefore is preferred.
MK2069-01 Loop Response and JItter
The MK2069-01 will reduce the transfer of phase jitter
existing on the input reference clock to the output clock. This
operation is known as jitter attenuation. The low-pass
frequency response of the VCXO PLL loop is the
mechanism that provides input jitter attenuation. Clock jitter,
more accurately called phase jitter, is the overall instability
of the clock period which can be measured in the time
domain using an oscilloscope, for instance. Jitter is
comprised of phase noise which can be represented in the
frequency domain. The phase noise of the input reference
clock is attenuated according to the VCXO PLL low-pass
frequency response curve. The response curve, and thus
the jitter attenuation characteristics, can be established
through the selection of external MK2069-01 passive
components and other device setting as explained in the
following section.
IDT® VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
MK2069-01
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
f(TCLK)
Where:
Where:
f(TCLK)
FT Divider = 1 to 64
RT Divider = 1 to 4
f(VCO) = 40 to 320 MHz
ST Divider = 2,4,8 or 16
Attenuation Characteristics
=
=
--------------------------- -
RT Divider
FT Divider
---------------------- -
ST Divider
f(VC0)
f(VCLK)
6
DF(VCLK)
Setting the VCXO PLL Loop Response.
The VCXO PLL loop response is determined both by fixed
device characteristics and by other characterizes set by the
user. This includes the values of R
shown in the External VCXO PLL Components figure on this
page.
The VCXO PLL loop bandwidth is approximated by:
The above equation calculates the “normalized” loop
bandwidth (denoted as “NBW”) which is approximately
equal to the - 3dB bandwidth. NBW does not take into
account the effects of damping factor or the second pole
imposed by C
approximation of filter performance.
To prevent jitter on VCLK due to modulation of the VCXO
PLL by the phase detector frequency, the following general
rule should be observed:
.
NBW(VCO PLL)
NBW(VCXO PLL)
The PLL loop damping factor is determined by:
Where:
R
I
K
SV Divider = 1,2,4,6,8,10,12 or 16
FV Divider = 1 to 4096
Where:
C
CP
O
S
S
= Value of resistor R
= VCXO Gain in Hz/V
= Value of capacitor C
=
= Charge pump current in amps
(see table on page 7)
(see table on page 8)
P
R
----- -
2
. It does, however, provide a useful
S
f(Phase Detector)
-------------------------------------- -
=
-------------------------------------------------------------- -
SV Divider
---------------------------------------------------------------------------- -
2
I
20
CP
SV Divider
R
VCXO AND SYNTHESIZER
S
C
S
S
S
in loop filter in Ohms
FV Divider
S
MK2069-01
in loop filter in Farads
, C
I
K
CP
O
S
, C
FV Divider
K
P
O
and R
REV K 051310
SET
as