MC88LV915TFN Freescale Semiconductor, MC88LV915TFN Datasheet - Page 5

• Manufacturer Part Number: MC88LV915TFN
• Description: IC DRV CLK PLL LV 100MHZ 28-PLCC
• Manufacturer: Freescale Semiconductor
• Type: Clock Driver, Fanout Distribution, Multiplexerr

Specifications of MC88LV915TFN

• Pll: Yes
• Input: TTL
• Output: CMOS, TTL
• Number Of Circuits: 1
• Ratio - Input:output: 3:8
• Differential - Input:output: No/No
• Frequency - Max: 100MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 100MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FREQUENCY SPECIFICATIONS (T
NOTE: Maximum Operating Frequency is guaranteed with the 88LV926 in a phase–locked condition.
AC CHARACTERISTICS
1. T
2. The T
3. Under equally loaded conditions and at a fixed temperature and voltage.
4. With V
5. The t
t
Outputs
t
(Q0–Q4, Q5, Q/2)
t
(2X_Q Output)
t
(2x_Q Output)
t
SYNC F
SYNC Feedback
t
(Rising) See Note 4
t
(Falling)
t
t
t
t
RISE/FALL
PULSE WIDTH
PULSE WIDTH
CYCLE
PD
SKEWr
SKEWf
SKEWall
LOCK
PZL
PHZ
Fmax (2X_Q)
Fmax (‘Q’)
MOTOROLA
C1 = 0.01 F.
2
CYCLE
5
Symbol
,t
4
PLZ
Symbol
3
3
PZL
3
PD
CC
5
in this spec is 1/Frequency at which the particular output is running.
, t
db
specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
fully powered–on, and an output properly connected to the FEEDBACK pin. t
PHZ
, t
k
PLZ
Maximum Operating Frequency, 2X_Q Output
Maximum Operating Frequency,
Q0–Q3 Outputs
minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is reached.
Rise/Fall Time, All Outputs
(Between 0.8 to 2.0V)
Output Pulse Width: Q0, Q1, Q2, Q3, Q4,
Q5, Q/2 @ V
Output Pulse Width:
2X_Q @ 1.5V
Cycle–to–Cycle Variation
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1 and
FEEDBACK Input Pins)
Output–to–Output Skew Between Outputs
Q0–Q4, Q/2 (Rising Edges Only)
Output–to–Output Skew Between Outputs
Q0–Q4 (Falling Edges Only)
Output–to–Output Skew 2X_Q, Q/2,
Q0–Q4 Rising, Q5 Falling
Time Required to Acquire Phase–Lock
From Time SYNC Input Signal is
Received
Output Enable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
Output Disable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
2x_Q @ V
(T
A
=0 C to +70 C, V
CC
CC
/2
Parameter
/2
A
= 0 C to 70 C; V
CC
Parameter
= 3.3V 0.3V, Load = 50 Terminated to V
100MHz
100MHz
100MHz
40MHz
40MHz
66MHz
80MHz
66MHz
80MHz
66MHz
80MHz
CC
= 3.3V
0.5t
0.5t
0.5t
0.5t
0.5t
t
t
t
t
CYCLE
CYCLE
CYCLE
CYCLE
(With 1M from RC1 to An V
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
0.3V)
–1.65
–1.45
–1.25
Min
0.5
1.0
3.0
3.0
—
—
—
– 600ps
– 300ps
– 300ps
– 400ps
– 0.5
– 1.5
– 1.0
– 1.0
– 1.0
1
LOCK
0.5t
0.5t
0.5t
0.5t
0.5t
t
t
t
t
CYCLE
CYCLE
CYCLE
CYCLE
maximum is with C1 = 0.1 F, t
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CC
–1.05
–0.85
–0.65
Max
500
750
750
2.0
10
14
14
/2)
+ 600ps
+ 300ps
+ 300ps
+ 400ps
+ 0.5
CC
+ 0.5
+ 0.5
+ 0.5
+ 0.5
)
Guaranteed Minimum
1
Unit
ms
ns
ns
ns
ns
ps
ps
ps
ns
ns
100
50
Into a 50 Load
Terminated to V
Into a 50 Load
Terminated to V
Into a 50 Load
Terminated to V
All Outputs Into a
Matched 50 Load
Terminated to V
All Outputs Into a
Matched 50 Load
Terminated to V
All Outputs Into a
Matched 50 Load
Terminated to V
Also Time to LOCK
Indicator High
Measured With the
PLL_EN Pin Low
Measured With the
PLL_EN Pin Low
LOCK
Condition
minimum is with
CC
CC
CC
CC
CC
CC
MHz
MHz
Unit
5
/2
/2
/2
/2
/2
/2