HSP45116AVC-52Z Intersil, HSP45116AVC-52Z Datasheet - Page 13

• Manufacturer Part Number: HSP45116AVC-52Z
• Description: IC OSCILLATOR/MOD NCO 160-MQFP
• Manufacturer: Intersil
• Type: Numerically Controlled Oscillator (NCO)r

Specifications of HSP45116AVC-52Z

• Frequency: 52MHz
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 184mA
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -

Rounding
The operation of the HSP45116A is identical to the
HSP45116 with the exception of a programmable rounding
option added for the data outputs. The added functionality
was achieved by using one of the HSP45116’s reserved
Configuration Registers to specify rounding precision and
replacing a V
RND is “high”, rounding is disabled, and the HSP45116A
functions as a pin-for-pin equivalent of the HSP45116. When
RND is active “low” rounding is enabled. The RND input
replaces V
seen in the Pinout Diagram.
The Round Control Register is loaded by placing the round
control value on C15-0, setting AD1-0 = 11, setting CS = 0,
and forcing a low to high transition on the WR input. The
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UNUSED
C15-8
CC
CC
ROUND CONTROL REGISTER
on PIN 75 of the 160 Lead MQFP package as
pin with a round enable (RND) input. When
ROUNDING
1101-1111
CMAC
0000
0001
0010
0100
0101
1000
1001
1010
C7-4
0011
0110
0111
1011
1100
13
ROUNDING
1101-1111
C3-0
ACC
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
0111
TABLE 6. ROUNDING CONTROL
HSP45116A
No Rounding
CMAC outputs rounded to most significant 20 bits, bit positions -2
ACC outputs rounded to most significant 20 bits, bit positions -2
CMAC outputs rounded to most significant 19 bits, bit positions -2
ACC outputs rounded to most significant 19 bits, bit positions -2
CMAC outputs rounded to most significant 18 bits, bit positions -2
ACC outputs rounded to most significant 18 bits, bit positions -2
CMAC outputs rounded to most significant 17 bits, bit positions -2
ACC outputs rounded to most significant 17 bits, bit positions -2
CMAC outputs rounded to most significant 16 bits, bit positions -2
ACC outputs rounded to most significant 16 bits, bit positions -2
CMAC outputs rounded to most significant 15 bits, bit positions -2
ACC outputs rounded to most significant 15 bits, bit positions -2
CMAC outputs rounded to most significant 14 bits, bit positions -2
ACC outputs rounded to most significant 14 bits, bit positions -2
CMAC outputs rounded to most significant 13 bits, bit positions -2
ACC outputs rounded to most significant 13 bits, bit positions -2
CMAC outputs rounded to most significant 12 bits, bit positions -2
ACC outputs rounded to most significant 12 bits, bit positions -2
CMAC outputs rounded to most significant 11 bits, bit positions -2
ACC outputs rounded to most significant 11 bits, bit positions -2
CMAC outputs rounded to most significant 10 bits, bit positions -2
ACC outputs rounded to most significant 10 bits, bit positions -2
CMAC outputs rounded to most significant 9 bits, bit positions -2
ACC outputs rounded to most significant 9 bits, bit positions -2
Undefined
rounding operation is determined by the least significant 8
bits loaded into the Control Register as shown in Table 6.
The least significant four bits (C3-0) loaded into the register
govern rounding of the real and imaginary outputs of the
Complex Accumulator (ACC). The next more significant four
bits (C7-4) govern the rounding of the complex outputs of the
complex multiply accumulator (CMAC). The real and
imaginary outputs from the CMAC or ACC are rounded to
the same precision. The rounding is perform by adding a
“one” to the bit position below the least significant bit desired
in the output. For example, for a configuration that rounds to
the most significant 20 bits of the CMAC output, a “one”
would be added to bit position 2
bit weightings).
ROUNDING OPERATION
-14
(See Figure 3 for output
4
4
4
4
4
4
4
4
4
4
4
4
4
to 2
to 2
to 2
to 2
to 2
to 2
to 2
to 2
to 2
to 2
to 2
4
to 2
4
4
4
4
4
4
4
4
4
4
to 2
to 2
to 2
to 2
to 2
to 2
to 2
to 2
to 2
to 2
to 2
to 2
-4
-6
-15
-14
-13
-12
-11
-10
-9
-8
-7
-5
-4
-6
-15
-14
-13
-12
-11
-10
-9
-8
-7
-5
May 7, 2007
FN4156.4