ISL12026IBZ Intersil, ISL12026IBZ Datasheet - Page 5

IC RTC/CALENDAR EEPROM 8-SOIC

ISL12026IBZ

Manufacturer Part Number
ISL12026IBZ
Description
IC RTC/CALENDAR EEPROM 8-SOIC
Manufacturer
Intersil
Type
Clock/Calendar/EEPROMr
Datasheets

Specifications of ISL12026IBZ

Memory Size
4K (512 x 8)
Time Format
HH:MM:SS (12/24 hr)
Date Format
YY-MM-DD-dd
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Clock Format
HH
Clock Ic Type
RTC
Interface Type
I2C, Serial
Memory Configuration
512 X 8
Supply Voltage Range
2.7V To 5.5V
Digital Ic Case Style
SOIC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL12026IBZ
Manufacturer:
INTELSEL
Quantity:
60
Part Number:
ISL12026IBZ
Manufacturer:
INTERSIL
Quantity:
20 000
Part Number:
ISL12026IBZ-T
Manufacturer:
INTERSIL
Quantity:
20 000
Part Number:
ISL12026IBZ-T
0
AC Electrical Specifications
NOTES:
10. t
Timing Diagrams
Bus Timing
Write Cycle Timing
3. IRQ/F
4. V
5. V
6. Bit BSW = 0 (Standard Mode), V
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the V
9. Parameter is not 100% tested.
SYMBOL
t
HD:STO
Cpin
sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
t
t
Cb
WC
WC
(OUTPUT TIMING)
DH
IL
DD
(INPUT TIMING)
= V
is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write
> V
SCL
SDA
OUT
DD
BAT
STOP Condition Hold Time for
Read, or Volatile Only Write
Output Data Hold Time
Capacitive Loading of SDA or SCL Total on-chip and off-chip.
SDA, and SCL Pin Capacitance
Non-volatile Write Cycle Time
x 0.1, V
Inactive.
SDA
SCL
+V
SDA
BATHYS
t
SU:STA
IH
PARAMETER
= V
8TH BIT OF LAST BYTE
DD
x 0.9, f
5
t
BAT
HD:STA
SCL
>= 1.8V
(Continued)
= 400kHz
t
F
t
DD SR-
SU:DAT
From SDA rising edge to SCL
falling edge. Both crossing 70%
of V
From SCL falling edge crossing
30% of V
30% to 70% of V
DD
specification must be followed.
TEST CONDITIONS
.
ACK
DD
t
HIGH
, until SDA enters the
ISL12026
DD
window.
t
LOW
t
HD:DAT
CONDITION
STOP
MIN
600
10
t
0
R
t
t
AA
WC
TYP
12
t
DH
CONDITION
START
MAX
400
10
20
t
BUF
UNITS
t
SU:STO
ms
ns
ns
pF
pF
t
HD:STO
October 23, 2006
NOTES
FN8231.5
10

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