TDA9955HL/17/C1,55 NXP Semiconductors, TDA9955HL/17/C1,55 Datasheet - Page 8

• Manufacturer Part Number: TDA9955HL/17/C1,55
• Description: IC ADC 8BIT 170MSPS 100-LQFP
• Manufacturer: NXP Semiconductors
• Type: Videor

Specifications of TDA9955HL/17/C1,55

• Resolution (bits): 8 b
• Sampling Rate (per Second): 170M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.75 V ~ 1.85 V, 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935281545557; TDA9955HL/17/C1; TDA9955HL/17/C1

NXP Semiconductors
TDA9955HL_1
Product data sheet
8.4 Activity detection
8.5 Sync detection and selection
8.6 Sync Detection Recognition and Separation
8.7 Clock generator
8.8 Sync multiplexers
The device detects the presence of signals on each sync input VSYNCx, HCSYNCx and
SOGx after slicing to indicate which kind of synchronization is present (where x equals 1
or 2):
A change of activity is notified by a HIGH-to-LOW transition on the VAI_N output pin.
The management of the synchronization is done by using vertical sync, horizontal sync
and analog composite sync on the green/luminance signal.
The device scans if a signal is present on the VSYNCx pin. If a signal is detected on this
pin, it means that there is a digital separated sync signal.
If no signal is detected on the HCSYNCx pin, the device scans if a signal is present on the
SOGx pin. If a signal is detected on this pin (and not on the HCSYNCx pin), it means that
there is an analog composite sync signal and the signal is sent into the sync recognition
function after slicing.
If the analog composite sync signal is on the green or on the luminance of the video
signal, the SOGx pin must be connected to this signal.
The Sync Detection Recognition and Separation (SDRS) allows to retrieve the horizontal
and the vertical synchronizations from composite sync. This composite sync comes from
the sync slicing function when the sync is on the green, luminance or CVBS signal or from
the digital composite sync on the HCSYNCx pin.
This function is able to eliminate any additional synchronization pulses which may be
added in the vertical blanking.
An internal PLL locked to the reference HSYNC signal from sync recognition provides
three different clocks, one pixel-clock for R/P
the VHREF timing generator, one formatter-clock at double frequency for the 4 : 2 : 2
formatter and one output-clock for the VCLK output pin.
The COAST signal, coming from SDRS and/or VHREF timing generator or coming from
the COAST input pin, allows to freeze the PLL phase frequency detector during the
vertical blanking.
A phase-locked flag indicates if the PLL is locked.
The sync multiplexer allow to select via the I
pulses signals HS, VS, CS and DE.
•
•
Digital separated syncs on VSYNCx and HCSYNCx
Analog composite sync on SOGx
Rev. 01 — 17 March 2008
Triple 8-bit analog-to-digital video converter for HDTV
2
R
C-bus the origin of the synchronization
, B/P
B
and G/Y channels sampling and for
TDA9955HL
© NXP B.V. 2008. All rights reserved.
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