ISL22316UFRT10Z-TK Intersil, ISL22316UFRT10Z-TK Datasheet - Page 5

• Manufacturer Part Number: ISL22316UFRT10Z-TK
• Description: IC POT DGTL 128TP LN LP 10-TDFN
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL22316UFRT10Z-TK

• Taps: 128
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Temperature Coefficient: 80 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-TDFN Exposed Pad
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL22316UFRT10Z-TK

Operating Specifications
EEPROM SPECIFICATION
SERIAL INTERFACE SPECIFICATIONS
Hysteresis SDA and SCL Input Buffer Hysteresis
SYMBOL
(Note 17)
(Note 18)
t
t
t
t
t
t
HD:STO
HD:STA
SU:DAT
HD:DAT
SU:STO
SU:STA
t
t
Cpin
t
f
HIGH
t
V
LOW
V
SCL
t
BUF
t
V
WC
t
Cb
DH
AA
t
t
sp
OL
R
IH
F
IL
EEPROM Endurance
EEPROM Retention
Non-volatile Write Cycle Time
A1, A0, SHDN, SDA, and SCL Input Buffer
LOW Voltage
A1, A0, SHDN, SDA, and SCL Input Buffer
HIGH Voltage
SDA Output Buffer LOW Voltage, Sinking
4mA
A1, A0, SHDN, SDA, and SCL Pin
Capacitance
SCL Frequency
Pulse Width Suppression Time at SDA and
SCL Inputs
SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of V
Time the Bus Must be Free Before the Start
of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup Time
STOP Condition Hold Time for Read, or
Volatile Only Write
Output Data Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL
PARAMETER
5
Over the recommended operating conditions, unless otherwise specified. (Continued)
Temperature T ≤ +55°C
Any pulse narrower than the max spec is
suppressed
SDA exits the 30% to 70% of V
SDA crossing 70% of V
condition, to SDA crossing 70% of V
during the following START condition
Measured at the 30% of V
Measured at the 70% of V
SCL rising edge to SDA falling edge; both
crossing 70% of V
From SDA falling edge crossing 30% of V
to SCL falling edge crossing 70% of V
From SDA exiting the 30% to 70% of V
window, to SCL rising edge crossing 30% of
V
From SCL rising edge crossing 70% of V
to SDA entering the 30% to 70% of V
window
From SCL rising edge crossing 70% of V
to SDA rising edge crossing 30% of V
From SDA rising edge to SCL falling edge;
both crossing 70% of V
From SCL falling edge crossing 30% of
V
V
From 30% to 70% of V
From 70% to 30% of V
Total on-chip and off-chip
CC
CC
CC
, until SDA enters the 30% to 70% of
window
ISL22316
TEST CONDITIONS
CC
CC
CC
CC
CC
CC
CC
during a STOP
crossing
crossing
CC
CC
window
CC
CC
, until
CC
CC
CC
CC
CC
CC
,
1,000,000
(Note 19)
0.05*V
0.7*V
0.1*Cb
0.1*Cb
1300
1300
1300
20 +
20 +
MIN
-0.3
600
600
600
100
600
50
10
0
0
0
CC
CC
(Note 5)
TYP
12
10
V
(Note 19)
0.3*V
CC
MAX
400
900
250
250
400
0.4
20
50
September 1, 2009
+ 0.3
CC
FN6186.2
Cycles
Years
UNIT
kHz
ms
pF
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
V
V