AD5173BRM2.5-RL7 Analog Devices Inc, AD5173BRM2.5-RL7 Datasheet - Page 17

• Manufacturer Part Number: AD5173BRM2.5-RL7
• Description: IC DGTL POT DUAL 2.5K OTP 10MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5173BRM2.5-RL7

• Rohs Status: RoHS non-compliant
• Taps: 256
• Resistance (ohms): 2.5K
• Number Of Circuits: 2
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 2.5K
• Number Of Elements: 2
• # Of Taps: 256
• Resistance (max): 2.5KOhm
• Power Supply Requirement: Single
• Interface Type: Serial (2-Wire/I2C)
• Single Supply Voltage (typ): 3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 10
• Lead Free Status / RoHS Status: Not Compliant

ESD PROTECTION
All digital inputs, SDA, SCL, AD0, and AD1, are protected with
a series input resistor and parallel Zener ESD structures, as
shown in Figure 43 and Figure 44.
TERMINAL VOLTAGE OPERATING RANGE
The AD5172/AD5173 V
boundary conditions for proper 3-terminal digital potenti-
ometer operation. Supply signals present on Terminal A,
Terminal B, and Terminal W that exceed V
clamped by the internal forward-biased diodes (see Figure 45).
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W (see Figure 45), it
is important to power V
Terminal A, Terminal B, and Terminal W. Otherwise, the diode
is forward-biased such that V
may affect the rest of the user’s circuit. The ideal power-up
sequence is GND, V
relative order of powering V
not important, as long as they are powered after V
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both the one-time pro-
gramming and normal operating voltage supplies are applied to
the same V
employ fuse link technology that requires 5.6 V to 5.8 V to blow
the internal fuses to achieve a given setting, but normal V
be 2.7 V to 5.5 V. Such dual-voltage requirements need isolation
between the supplies if V
The fuse programming supply (either an on-board regulator or
Figure 45. Maximum Terminal Voltages Set by V
DD
Figure 44. ESD Protection of Resistor Terminals
terminal of the device. The AD5172/AD5173
Figure 43. ESD Protection of Digital Pins
DD
, digital inputs, and then V
A, B, W
GND
GND
DD
DD
DD
340Ω
/GND before applying voltage to
to GND power supply defines the
is lower than the required V
A
, V
DD
is powered unintentionally and
B
LOGIC
, V
W
, and the digital inputs is
V
A
W
B
GND
DD
DD
or GND are
DD
A
and GND
/V
DD
/GND.
B
/V
DD_OTP
W
. The
DD
can
Rev. H | Page 17 of 24
.
rack-mount power supply) must be rated at 5.6 V to 5.8 V and
must be able to provide a 100 mA transient current for 400 ms
for successful one-time programming. When programming
is completed, the V
normal operation at 2.7 V to 5.5 V; the device consumes only
microamps of current.
For example, for those who operate their systems at 2.7 V, use of
the bidirectional, low threshold, P-channel MOSFETs is recom-
mended for the isolation of the supply. As shown in Figure 46,
this assumes that the 2.7 V system voltage is applied first and
that the P1 and P2 gates are pulled to ground, thus turning on
P1 and then P2. As a result, V
approaches 2.7 V. When the AD5172/AD5173 setting is found,
the factory tester applies the V
MOSFET gates, thus turning P1 and P2 off. To program the
AD5172/AD5173 while the 2.7 V source is protected, execute
the OTP command at this time. When the OTP is completed,
the tester withdraws the V
or AD5173 is fixed permanently.
The AD5172/AD5173 achieve the OTP function by blowing
internal fuses. Always apply the 5.6 V to 5.8 V one-time pro-
gram voltage requirement at the first fuse programming attempt.
Failure to comply with this requirement may lead to changing
the fuse structures, rendering programming inoperable.
Care should be taken when SCL and SDA are driven from a low
voltage logic controller. Users must ensure that the logic high
level is between 0.7 V × V
Poor PCB layout introduces parasitics that can affect fuse
programming. Therefore, it is recommended to add a 1 μF to
10 μF tantalum capacitor in parallel with a 1 nF ceramic capacitor
as close as possible to the VDD pin. The type and value chosen for
both capacitors are important. These capacitors work together to
provide both fast responsiveness and large supply current handling
with minimum supply droop during transients. As a result,
these capacitors increase the OTP programming success by not
inhibiting the proper energy needed to blow the internal fuses.
Additionally, C1 minimizes transient disturbance and low
frequency ripple, whereas C2 reduces high frequency noise
during normal operation.
5.7V
2.7V
Figure 46. Isolate 5.7 V OTP Supply from 2.7 V Normal Operating Supply
10kΩ
R1
P1 = P2 = FDV302P, NDS0610
P1
DD_OTP
APPLY FOR OTP ONLY
P2
10µF
supply must be removed to allow
DD
DD_OTP
C1
and V
DD
DD_OTP
, and the setting of the AD5172
0.1µF
of the AD5172/AD5173
C2
DD
to both the V
+ 0.5 V.
AD5172/AD5173
V
DD
AD5172/
AD5173
DD
and the