IC POT DIG QUAD 100K 8B 24TSSOP

AD8403ARU100-REEL

Manufacturer Part NumberAD8403ARU100-REEL
DescriptionIC POT DIG QUAD 100K 8B 24TSSOP
ManufacturerAnalog Devices Inc
AD8403ARU100-REEL datasheet
 


Specifications of AD8403ARU100-REEL

Rohs StatusRoHS non-compliantTaps256
Resistance (ohms)100KNumber Of Circuits4
Temperature Coefficient500 ppm/°C TypicalMemory TypeVolatile
InterfaceSPI, 3-Wire SerialVoltage - Supply2.7 V ~ 5.5 V
Operating Temperature-40°C ~ 125°CMounting TypeSurface Mount
Package / Case24-TSSOPResistance In Ohms100K
Number Of Elements4# Of Taps256
Resistance (max)100KOhmPower Supply RequirementSingle
Interface TypeSerial (3-Wire/SPI)Single Supply Voltage (typ)3/5V
Dual Supply Voltage (typ)Not RequiredVSingle Supply Voltage (min)2.7V
Single Supply Voltage (max)5.5VDual Supply Voltage (min)Not RequiredV
Dual Supply Voltage (max)Not RequiredVOperating Temp Range-40C to 125C
Operating Temperature ClassificationAutomotiveMountingSurface Mount
Pin Count24Package TypeTSSOP
For Use WithAD8403EVAL - BOARD EVAL FOR AD8403  
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Parameter
6, 10
DYNAMIC CHARACTERISTICS
Bandwidth −3 dB
Total Harmonic Distortion
V
Settling Time
W
Resistor Noise Voltage
11
Crosstalk
1
Typicals represent average readings at 25°C and V
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. See the test circuit in Figure 38. I
I
= 2.5 mA for V
= 5 V for 1 kΩ version.
W
DD
3
V
= V
, wiper (V
) = no connect.
AB
DD
W
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37.
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal.
The remaining resistor terminals are left open circuit.
7
Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8
Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See Figure 28 for a plot of I
9
P
is calculated from (I
× V
). CMOS logic level inputs result in minimum power dissipation.
DISS
DD
DD
10
All dynamic characteristics use V
= 5 V.
DD
11
Measured at a V
pin where an adjacent V
pin is making a full-scale voltage change.
W
W
Symbol
Conditions
BW_1 K
R = 1 kΩ
THD
V
= 1 V rms + 2 V dc, V
= 2 V dc, f = 1 kHz
W
A
B
t
V
= V
, V
= 0 V, ±1% error band
S
A
DD
B
e
= 500 Ω, f = 1 kHz, RS = 0
R
NWB
WB
C
V
= V
, V
= 0 V
T
A
DD
B
= 5 V.
DD
Rev. E | Page 9 of 32
AD8400/AD8402/AD8403
1
Min
Typ
Max
Unit
5,000
kHz
0.015
%
0.5
μs
3
nV/√Hz
−65
dB
= 500 μA for V
= 3 V and
W
DD
= V
and V
= 0 V.
A
DD
B
vs. logic voltage.
DD