X9401WS24IZ-2.7T1 Intersil, X9401WS24IZ-2.7T1 Datasheet - Page 3

IC POT DGTL QUAD 10K OHM 24-SOIC

X9401WS24IZ-2.7T1

Manufacturer Part Number
X9401WS24IZ-2.7T1
Description
IC POT DGTL QUAD 10K OHM 24-SOIC
Manufacturer
Intersil
Series
XDCP™r
Datasheet

Specifications of X9401WS24IZ-2.7T1

Taps
64
Resistance (ohms)
10K
Number Of Circuits
4
Temperature Coefficient
300 ppm/°C Typical
Memory Type
Non-Volatile
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (7.5mm Width)
Resistance In Ohms
10K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
X9401WS24IZ-2.7T1TR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
X9401WS24IZ-2.7T1
Manufacturer:
IDT
Quantity:
3 067
Pinouts
Pin Descriptions
15, 22,
16, 23
14, 21
13, 24
SOIC
PIN #
3, 10,
4, 11,
7, 19
20, 8
2, 9,
17
18
12
5
6
1
TSSOP
10, 17
PIN #
21, 4,
9, 16,
20, 3,
22, 5,
1, 13
14, 2
8, 15
7, 18
23
11
24
12
19
V
V
6
V
V
V
V
W1
W2
V
V
H1
H2
L1
L2
V
V
V
V
HOLD
W0
W1
H0
H1
/R
/R
L0
L1
/R
/R
/R
/R
SCK
V
/R
/R
W1
NC
W2
V
/R
/R
A
H1
SS
H2
/R
/R
L1
L2
V
V
V
SI
V
WP
V
1
V
W0
W0
CS
W1
CC
V
W2
H0
A
H1
SS
L0
L1
H2
SI
H0
L0
1
L2
10
11
12
1
2
3
4
5
6
7
8
9
/R
/R
/R
/R
/R
10
11
12
/R
SYMBOL
1
2
3
4
5
6
7
8
9
W0,
A
W2,
H2
H0,
L0,
HOLD
SI, S0
L2,
(24 LD TSSOP)
SCK
0
V
V
WP
NC
(24 LD SOIC)
CS
, V
CC
SS
- A
TOP VIEW
TOP VIEW
V
V
V
V
V
H1
L1
H3
W1
X9401
X9401
L3
W3
1
/R
/R
/R
/R
/R
/R
3
L1
H1,
L3
H3
W1,
W3
,
,
Chip select
Serial Clock
Serial Data
Device Address
Potentiometer end
terminals
Wipers
Hardware Write Protection
Hardware Hold
System Supply Voltage
System Ground
No Connection
24
23
22
21
20
19
18
17
16
15
14
13
24
23
22
21
20
19
18
17
16
15
14
13
NC
V
V
V
A
S0
HOLD
SCK
V
V
V
NC
DESCRIPTION
WP
CS
V
V
V
V
NC
V
V
V
A
S0
L3
H3
W3
0
L2
H2
W2
CC
W0
H0
L0
L3
H3
W3
0
/R
/R
/R
/R
/R
/R
/R
/R
/R
/R
/R
/R
L3
L2
H3
H2
W3
W2
L0
L3
H0
H3
W0
W3
X9401
Device Description
The X9401 is a highly integrated microcircuit incorporating
four resistor arrays and their associated registers and
counters and the serial interface logic providing direct
communication between the host and the XDCP
potentiometers.
Serial Interface
The X9401 supports the SPI interface hardware
conventions. The device is accessed via the SI input with
data clocked in on the rising SCK. CS must be LOW and the
HOLD and WP pins must be HIGH during the entire
operation.
The SO and SI pins can be connected together, since they
have three state outputs. This can help to reduce system pin
count.
Array Description
The X9401 is comprised of four resistor arrays. Each array
contains 63 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (V
and V
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (V
output. Within each individual array only one switch may be
turned on at a time.
These switches are controlled by a Wiper Counter Register
(WCR). The six bits of the WCR are decoded to select, and
enable, one of sixty-four switches.
Wiper Counter Register (WCR)
The X9401 contains four Wiper Counter Registers, one for
each XDCP potentiometer. The WCR is equivalent to a
serial-in, parallel-out register/counter with its outputs
decoded to select one of sixty-four switches along its resistor
array. The contents of the WCR can be altered in four ways:
it may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be written
indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register or
Global XFR Data Register instructions (parallel load); it can
be modified one step at a time by the Increment/Decrement
instruction. Finally, it is loaded with the contents of its data
register zero (R0) upon power-up.
The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9401 is powered-down.
Although the register is automatically loaded with the value
in R
present at power-down. The wiper position must be stored in
R
0
to insure restoring the wiper position after power-up.
0
upon power-up, this may be different from the value
L
/R
L
inputs).
October 13, 2009
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FN8190.4
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/R
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