CONV D/A 12BIT MICRO PWR TSOT236

DAC121S101CIMK/NOPB

Manufacturer Part NumberDAC121S101CIMK/NOPB
DescriptionCONV D/A 12BIT MICRO PWR TSOT236
ManufacturerNational Semiconductor
SeriesPowerWise®
DAC121S101CIMK/NOPB datasheet
 


Specifications of DAC121S101CIMK/NOPB

Settling Time12µsNumber Of Bits12
Data InterfaceDSP, MICROWIRE™, QSPI™, Serial, SPI™Number Of Converters1
Voltage Supply SourceSingle SupplyPower Dissipation (max)1.72mW
Operating Temperature-40°C ~ 105°CMounting TypeSurface Mount
Package / CaseTSOT-23-6, TSOT-6Number Of Channels1
Resolution12bInterface TypeSerial (3-Wire, SPI, QSPI, Microwire)
Single Supply Voltage (typ)3.3/5VDual Supply Voltage (typ)Not RequiredV
ArchitectureResistor-StringPower Supply RequirementSingle
Output TypeVoltageIntegral Nonlinearity Error±8LSB
Single Supply Voltage (min)2.7VSingle Supply Voltage (max)5.5V
Dual Supply Voltage (min)Not RequiredVDual Supply Voltage (max)Not RequiredV
Operating Temp Range-40C to 105COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count6
Package TypeTSOTFor Use WithDAC121S101EVAL - BOARD EVALUATION DAC121S101
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther namesDAC121S101CIMK
DAC121S101CIMKTR
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Ordering Information
Order Numbers
DAC121S101CIMM
DAC121S101CIMMX
DAC121S101CIMK
DAC121S101CIMKX
DAC121S101QCMK
DAC121S101QCMKX
DAC121S101EVAL
Block Diagram
Pin Descriptions
TSOT
MSOP
(SOT-23)
Symbol
Pin No.
Pin No.
V
1
4
OUT
2
8
GND
V
3
1
A
D
4
7
IN
5
6
SCLK
6
5
SYNC
2, 3
NC
www.national.com
Temperature Range
Package
MSOP
−40°C
T
+105°C
A
MSOP T/R
−40°C
T
+105°C
A
TSOT
−40°C
T
+105°C
A
TSOT T/R
−40°C
T
+105°C
A
TSOT
−40°C
T
+125°C
A
TSOT T/R
−40°C
T
+125°C
A
Evaluation Board
TSOT
DAC Analog Output Voltage.
Ground reference for all on-chip circuitry.
Power supply and Reference input. Should be decoupled to GND.
Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK
after the fall of SYNC.
Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin.
Frame synchronization input for the data input. When this pin goes low, it enables the input
shift register and data is transferred on the falling edges of SCLK. The DAC is updated on
the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
No Connect. There is no internal connection to these pins.
2
Top Mark
Feature
X60C
X61C
AEC-Q100 Grade 1
X61Q
Qualified; Automotive
Grade Production Flow
20114903
Description