CS43L22-CNZ Cirrus Logic Inc, CS43L22-CNZ Datasheet - Page 29

IC DAC W/HDPN & SPKR AMPS 40QFN

CS43L22-CNZ

Manufacturer Part Number
CS43L22-CNZ
Description
IC DAC W/HDPN & SPKR AMPS 40QFN
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS43L22-CNZ

Package / Case
40-QFN
Number Of Bits
24
Data Interface
Serial
Number Of Converters
1
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Conversion Rate
96 KSPS
Resolution
24 bit
Interface Type
Serial
Operating Supply Voltage
1.8 V or 2.5 V
Operating Temperature Range
+ 85 C
Mounting Style
SMD/SMT
Number Of Dac Outputs
2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1529 - BOARD EVAL FOR CS43L22
Power Dissipation (max)
-
Settling Time
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1650

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS43L22-CNZ
Manufacturer:
CRYSTAL
Quantity:
170
Part Number:
CS43L22-CNZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
CS43L22-CNZR
Manufacturer:
CIRRUSLOG
Quantity:
1 183
DS792F2
4.6
Serial Port Clocking
The CS43L22 serial audio interface port operates either as a slave or master, determined by the M/S bit. It
accepts externally generated clocks in Slave Mode and will generate synchronous clocks derived from an
input master clock (MCLK) in Master Mode. Refer to the tables below for the required setting in register 05h
and 06h associated with a given MCLK and sample rate.
Referenced Control
M/S...................................
Register 05h......................
Register 06h......................
12.2880
11.2896
18.4320
(Slave
Mode
ONLY)
16.9344
(Slave
Mode
ONLY)
12.0000
24.0000
MCLK
(MHz)
Sample Rate,
*22.0588...
*88.2353...
*22.0588...
*88.2353...
*11.0294...
*44.1176...
*11.0294...
*44.1176...
*8.0182...
Fs (kHz)
12.0000
16.0000
24.0000
32.0000
48.0000
96.0000
11.0250
22.0500
44.1000
88.2000
12.0000
16.0000
24.0000
32.0000
48.0000
96.0000
11.0250
22.0500
44.1000
88.2000
12.0000
16.0000
24.0000
32.0000
48.0000
96.0000
12.0000
16.0000
24.0000
32.0000
48.0000
96.0000
8.0000
8.0000
8.0000
8.0000
Register Location
“Master/Slave Mode” on page 40
“Clocking Control (Address 05h)” on page 38
“Interface Control 1 (Address 06h)” on page 40
SPEED[1:0]
(AUTO=’0’b)
11
11
10
10
01
01
00
11
10
01
00
11
11
10
10
01
01
00
11
11
10
01
00
11
11
11
10
10
10
01
01
01
00
00
11
11
11
10
10
10
01
01
01
00
00
Confidential Draft
3/4/10
32kGROUP
1
0
1
0
1
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
VIDEOCLK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RATIO[1:0]
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
10
00
00
00
00
01
01
01
01
01
01
01
01
01
01
01
01
01
01
11
11
11
11
11
11
11
11
CS43L22
MCLKDIV2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
29

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