CS43L22-CNZ Cirrus Logic Inc, CS43L22-CNZ Datasheet - Page 39

• Manufacturer Part Number: CS43L22-CNZ
• Description: IC DAC W/HDPN & SPKR AMPS 40QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS43L22-CNZ

• Package / Case: 40-QFN
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 1.8 V or 2.5 V
• Operating Temperature Range: + 85 C
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1529 - BOARD EVAL FOR CS43L22
• Power Dissipation (max): -
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1650

DS792F2
7.4.2
7.4.3
7.4.4
7.4.5
Speed Mode
Configures the speed mode of the DAC in Slave Mode and sets the appropriate MCLK divide ratio for
LRCK and SCLK in Master Mode.
Notes:
1. Slave/Master Mode is determined by the M/S bit in
2. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit
3. These bits are ignored when the AUTO bit
32kHz Sample Rate Group
Specifies whether or not the input/output sample rate is 8 kHz, 16 kHz or 32 kHz.
27 MHz Video Clock
Specifies whether or not the external MCLK frequency is 27 MHz
Internal MCLK/LRCK Ratio
Configures the internal MCLK/LRCK ratio.
32kGROUP
0
1
Application:
VIDEOCLK
0
1
Application:
SPEED[1:0]
00
01
10
11
Application:
RATIO[1:0]
00
01
10
11
Application:
(“32kHz Sample Rate Group” on page
page
affect dynamic range performance in the typical audio band. Refer to the referenced application for
more information.
39) and RATIO[1:0] bits
Slave Mode
Serial Port Speed
Double-Speed Mode (DSM - 50 kHz -100 kHz Fs)
Single-Speed Mode (SSM - 4 kHz -50 kHz Fs)
Half-Speed Mode (HSM - 12.5kHz -25 kHz Fs)
Quarter-Speed Mode (QSM - 4 kHz -12.5 kHz Fs)
“Serial Port Clocking” on page 29
8 kHz, 16 kHz or 32 kHz sample rate?
No
Yes
“Serial Port Clocking” on page 29
27 MHz MCLK?
No
Yes
“Serial Port Clocking” on page 29
Internal MCLK Cycles per LRCK
128
125
132
136
“Serial Port Clocking” on page 29
(“Internal MCLK/LRCK Ratio” on page
Confidential Draft
39) and/or the VIDEOCLK bit
3/4/10
(“Auto-Detect” on page
“Master/Slave Mode” on page
Master Mode
MCLK/LRCK Ratio
512
256
128
128
SCLK/LRCK Ratio in Master Mode
64
62
66
68
38) is enabled.
39). Low sample rates may also
(“27 MHz Video Clock” on
SCLK/LRCK Ratio
64
64
64
64
40.
CS43L22
39