CS43L22-CNZ Cirrus Logic Inc, CS43L22-CNZ Datasheet - Page 33

• Manufacturer Part Number: CS43L22-CNZ
• Description: IC DAC W/HDPN & SPKR AMPS 40QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS43L22-CNZ

• Package / Case: 40-QFN
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 1.8 V or 2.5 V
• Operating Temperature Range: + 85 C
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1529 - BOARD EVAL FOR CS43L22
• Power Dissipation (max): -
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1650

DS792F2
5. CONTROL PORT OPERATION
5.1
SCL
SDA
SDA
SCL
START
The control port is used to access the registers allowing the CS43L22 to be configured for the desired op-
erational modes and formats. The operation of the control port may be completely asynchronous with re-
spect to the audio sample rates. However, to avoid potential interference problems, the control port pins
should remain static if no operation is required.
The control port operates using an I²C interface with the CS43L22 acting as a slave device.
I²C Control
SDA is a bidirectional data line. Data is clocked into and out of the device by the clock, SCL. The AD0 pin
sets the LSB of the chip address; ‘0’ when connected to DGND, ‘1’ when connected to VL. This pin may be
driven by a host controller or directly connected to VL or DGND. The AD0 pin state is sensed and the LSB
of the chip address is set upon the release of the RESET signal (a low-to-high transition).
The signal timings for a read and write cycle are shown in
fined as a falling transition of SDA while the clock is high. A Stop condition is defined as a rising transition
of SDA while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent
to the CS43L22 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read,
low for a write).
The upper 6 bits of the address field are fixed at 100101. To communicate with the CS43L22, the chip ad-
dress field, which is the first byte sent to the CS43L22, should match 100101 followed by the setting of the
AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory
Address Pointer (MAP), which selects the register to be read or written. If the operation is a read, the con-
tents of the register pointed to by the MAP will be output. Setting the auto-increment bit in MAP allows suc-
cessive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK
bit is output from the CS43L22 after each input byte is read and is input to the CS43L22 from the microcon-
troller after each transmitted byte.
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
START
0
CHIP ADDRESS (WRITE)
1
Figure
1
0
0
1
2
CHIP ADDRESS (WRITE)
0
1
0
3
1
17, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
0
2
4
0 1 AD0 0
1
5
3
0
6
4
1
7
5
ACK
AD0
8
6
9
INCR
7
Figure 16. Control Port Timing, I²C Write
Figure 17. Control Port Timing, I²C Read
0
10 11
ACK
6
8
5
INCR
MAP BYTE
9
12 13 14 15
4
10 11
6
3
Confidential Draft
MAP BYTE
5
2
12
4
1
13 14 15
16
0
3
ACK
STOP
2
17 18
3/4/10
START
1
16 17 18
0
19
ACK
1
20 21 22 23 24
CHIP ADDRESS (READ)
0
7
0
Figure 16
19
6
DATA
1
0
24 25
1
1 AD0 1
0
25
ACK
and
26
26 27 28
27 28
ACK
7
Figure
DATA +1
6
7
DATA
1
0
17. A Start condition is de-
ACK
0
DATA +1
7
7
DATA +n
0
6
1
DATA + n
7
CS43L22
0
ACK
0
STOP
ACK
NO
STOP
33