CS43L22-CNZ Cirrus Logic Inc, CS43L22-CNZ Datasheet - Page 32

• Manufacturer Part Number: CS43L22-CNZ
• Description: IC DAC W/HDPN & SPKR AMPS 40QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS43L22-CNZ

• Package / Case: 40-QFN
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 1.8 V or 2.5 V
• Operating Temperature Range: + 85 C
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1529 - BOARD EVAL FOR CS43L22
• Power Dissipation (max): -
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1650

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4.11
4. Wait at least 100 µs.
5. MCLK may be removed at this time.
6. To achieve the lowest operating quiescent current, bring RESET low. All control port registers will be
Required Initialization Settings
Various sections in the device must be adjusted by implementing the initialization settings shown below after
power-up sequence step 3. All performance and power consumption measurements were taken with the
following settings:
1. Write 0x99 to register 0x00.
2. Write 0x80 to register 0x47.
3. Write ‘1’b to bit 7 in register 0x32.
4. Write ‘0’b to bit 7 in register 0x32.
5. Write 0x00 to register 0x00.
The device will be fully powered down after this 100 µs delay. Prior to the removal of the master clock
(MCLK), this delay of at least 100 µs must be implemented after step
of the DAC’s power down sequence.
A disruption in the device’s power down sequence (i.e. removing the MCLK signal before this 100 µs
delay) has consequences on both the headphone and PWM speaker amplifiers: The charge pump may
stop abruptly, causing the headphone amplifiers to drive the outputs up to the +VHP supply. Also, the
last state of each ‘+’ and ‘-’ PWM output terminal before the premature removal of MCLK could randomly
be held at either VP or AGND. When this event occurs, it is possible for each PWM terminal to output
opposing potentials, creating a DC source into the speaker voice coil.
The disruption of the device’s power down sequence may also cause clicks and pops on the output of
the DAC’s as the modulator holds the last output level before the MCLK signal was removed.
reset to their default state.
Confidential Draft
3/4/10
3
to avoid premature disruption
CS43L22
DS792F2