AD5390BSTZ-5 Analog Devices Inc, AD5390BSTZ-5 Datasheet - Page 34

• Manufacturer Part Number: AD5390BSTZ-5
• Description: IC DAC 14BIT I2C 16CH 52-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD5390BSTZ-5

• Data Interface: I²C, Serial
• Design Resources: 8 to 16 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5390/1/2 (CN0029) AD5390/91/92 Channel Monitor Function (CN0030)
• Settling Time: 8µs
• Number Of Bits: 14
• Number Of Converters: 16
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 35mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Resolution (bits): 14bit
• Sampling Rate: 125kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analogue: 4.5V To 5.5V
• Supply Voltage Range - Digital: 2.7V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD5390EBZ - BOARD EVALUATION FOR AD5390
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD5390/AD5391/AD5392
HARDWARE FUNCTIONS
RESET FUNCTION
Bringing the RESET line low resets the contents of all internal
registers to their power-on reset state. RESET is a negative edge-
sensitive input. The default corresponds to m at full scale and
c at zero scale. The contents of all DAC registers are cleared by
setting the outputs to 0 V. This sequence takes 270 μs maximum.
The falling edge of RESET initiates the reset process. BUSY goes
low for the duration, returning high when RESET is complete.
While BUSY is low, all interfaces are disabled and all LDAC
pulses are ignored. When BUSY returns high, the part resumes
normal operation, and the status of the RESET pin is ignored
until the next falling edge is detected.
ASYNCHRONOUS CLEAR FUNCTION
CLR is negative-edge-triggered and BUSY goes low for the
duration of the CLR execution. Bringing the CLR line low
clears the contents of the DAC registers to the data contained in
the user-configurable CLR register and sets the analog outputs
accordingly. This function can be used in system calibration
to load zero scale and full scale to all channels together. The
execution time for a CLR is 20 μs on the AD5390/AD5391 and
15 μs on the AD5392.
BUSY AND LDAC FUNCTIONS
BUSY is a digital CMOS output indicating the status of the
AD539x devices. BUSY goes low during internal calculations
of x2 data. If LDAC is taken low while BUSY is low, this event
is stored. The user can hold the LDAC input permanently low
and, in this case, the DAC outputs update immediately after
BUSY goes high. BUSY also goes low during a power-on reset
and when a falling edge is detected on the RESET pin. During
this time, all interfaces are disabled and any events on LDAC
are ignored.
The AD539x products contain an extra feature whereby a DAC
register is not updated unless its x2 register has been written
to since the last time LDAC was brought low. Normally, when
LDAC is brought low, the DAC registers are filled with the
contents of the x2 registers. However, these devices update the
DAC register only if the x2 data has changed, thereby removing
unnecessary digital crosstalk.
Rev. C | Page 34 of 40
POWER-ON RESET
The AD539x products contain a power-on reset generator
and state machine. The power-on reset resets all registers to a
predefined state, and the analog outputs are configured as high
impedance outputs. The BUSY pin goes low during the power-
on reset sequence, preventing data writes to the device.
POWER-DOWN
The AD539x products contain a global power-down feature that
puts all channels into a low power mode, reducing the analog
power consumption to 1 μA maximum and the digital power
consumption to 20 μA maximum. In power-down mode, the
output amplifier can be configured as a high impedance output
or to provide a 100 kΩ load to ground. The contents of all
internal registers are retained in power-down mode. When
exiting power-down, the settling time of the amplifier elapses
before the outputs settle to their correct value.
MICROPROCESSOR INTERFACING
AD539x to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is
configured for master mode (MSTR = 1), clock polarity bit
(CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)—see
the 68HC11 User Manual. SCK of the MC68HC11 drives the
SCLK of the AD539x, the MOSI output drives the serial data
line (DIN) of the AD539x, and the MISO input is driven from
D
data is being transmitted to the AD539x, the SYNC line is taken
low (PC7). Data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the MC8HC11 is trans-
mitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle.
OUT
. The SYNC signal is derived from a port line (PC7). When
MC68HC11
Figure 37. AD539x-MC68HC11 Interface
MISO
MOSI
SCK
PC7
DV
DD
RESET
SDO
DIN
SCLK
SYNC
SPI/I
AD539x
2
C