AD9754ARU Analog Devices Inc, AD9754ARU Datasheet - Page 15

• Manufacturer Part Number: AD9754ARU
• Description: IC DAC 14BIT 125MSPS 28-TSSOP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9754ARU

• Mounting Type: Surface Mount
• Rohs Status: RoHS non-compliant
• Settling Time: 35ns
• Number Of Bits: 14
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 220mW
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• Resolution (bits): 14bit
• No. Of Pins: 28
• Update Rate: 125MSPS
• Peak Reflow Compatible (260 C): No
• No. Of Bits: 14 Bit
• Leaded Process Compatible: No
• Voltage Rating: 5V
• Number Of Channels: 1
• Resolution: 14b
• Interface Type: Parallel
• Single Supply Voltage (typ): 5V
• Dual Supply Voltage (typ): Not RequiredV
• Power Supply Requirement: Analog and Digital
• Output Type: Current
• Single Supply Voltage (min): 4.5V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / Rohs Status: Not Compliant

SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
Figure 30 shows the AD9754 configured to provide a unipolar
output range of approximately 0 V to +0.5 V for a doubly termi-
nated 50
20 mA flows through the equivalent R
R
or IOUTB. The unused output (IOUTA or IOUTB) can be
connected to ACOM directly or via a matching R
values of I
tive compliance range is adhered to. One additional consider-
ation in this mode is the integral nonlinearity (INL) as discussed
in the Analog Output section of this data sheet. For optimum
INL performance, the single-ended, buffered voltage output
configuration is suggested.
SINGLE-ENDED BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 31 shows a buffered single-ended output configuration in
which the op amp U1 performs an I-V conversion on the AD9754
output current. U1 maintains IOUTA (or IOUTB) at a virtual
ground, thus minimizing the nonlinear output impedance effect
on the DAC’s INL performance as discussed in the Analog
Output section. Although this single-ended configuration typi-
cally provides the best dc linearity performance, its ac distortion
performance at higher DAC update rates may be limited by
U1’s slewing capabilities. U1 provides a negative unipolar
output voltage and its full-scale output voltage is simply the
product of R
within U1’s voltage output swing capabilities by scaling I
and/or R
result with a reduced I
required to sink will be subsequently reduced.
REV. A
LOAD
Figure 30. 0 V to +0.5 V Unbuffered Voltage Output
AD9754
represents the equivalent load resistance seen by IOUTA
Figure 31. Unipolar Buffered Voltage Output
FB
IOUTA
IOUTB
AD9754
OUTFS
. An improvement in ac distortion performance may
cable since the nominal full-scale current, I
IOUTA
IOUTB
FB
22
21
and I
and R
I
OUTFS
22
21
OUTFS
I
OUTFS
LOAD
OUTFS
= 10mA
200
25
= 20mA
. The full-scale output should be set
can be selected as long as the posi-
since the signal current U1 will be
50
U1
C
200
R
OPT
FB
LOAD
of 25 . In this case,
V
V
OUTA
OUT
50
= I
= 0 TO +0.5V
LOAD
OUTFS
. Different
OUTFS
OUTFS
R
FB
, of
–15–
POWER AND GROUNDING CONSIDERATIONS, POWER
SUPPLY REJECTION
Many applications seek high speed and high performance under
less than ideal operating conditions. In these circuits, the imple-
mentation and construction of the printed circuit board design
is as important as the circuit design. Proper RF techniques must
be used for device selection, placement and routing as well as
power supply bypassing and grounding to ensure optimum
performance. Figures 39-44 illustrate the recommended printed
circuit board ground, power and signal plane layouts which are
implemented on the AD9754 evaluation board.
One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution
(i.e., AVDD, DVDD). This is referred to as Power Supply
Rejection Ratio (PSRR). For dc variations of the power supply,
the resulting performance of the DAC directly corresponds to a
gain error associated with the DAC’s full-scale current, I
AC noise on the dc supplies is common in applications where
the power distribution is generated by a switching power supply.
Typically, switching power supply noise will occur over the
spectrum from tens of kHz to several MHz. PSRR vs. frequency
of the AD9754 AVDD supply, over this frequency range, is
given in Figure 32.
Note that the units in Figure 32 are given in units of (amps out)/
(volts in). Noise on the analog power supply has the effect of
modulating the internal switches, and therefore the output
current. The voltage noise on the dc power, therefore, will be
added in a nonlinear manner to the desired I
relative different sizes of these switches, PSRR is very code
dependent. This can produce a mixing effect which can modu-
late low frequency power supply noise to higher frequencies.
Worst case PSRR for either one of the differential DAC outputs
will occur when the full-scale current is directed towards that
output. As a result, the PSRR measurement in Figure 32 repre-
sents a worst case condition in which the digital inputs remain
static and the full-scale output current of 20 mA is directed to
the DAC output being measured.
Figure 32. Power Supply Rejection Ratio of AD9754
90
80
70
60
0.26
FREQUENCY – MHz
0.5
0.75
OUT
AD9754
. Due to the
1.0
OUTFS
.