AD9754ARU Analog Devices Inc, AD9754ARU Datasheet - Page 9

• Manufacturer Part Number: AD9754ARU
• Description: IC DAC 14BIT 125MSPS 28-TSSOP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9754ARU

• Mounting Type: Surface Mount
• Rohs Status: RoHS non-compliant
• Settling Time: 35ns
• Number Of Bits: 14
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 220mW
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• Resolution (bits): 14bit
• No. Of Pins: 28
• Update Rate: 125MSPS
• Peak Reflow Compatible (260 C): No
• No. Of Bits: 14 Bit
• Leaded Process Compatible: No
• Voltage Rating: 5V
• Number Of Channels: 1
• Resolution: 14b
• Interface Type: Parallel
• Single Supply Voltage (typ): 5V
• Dual Supply Voltage (typ): Not RequiredV
• Power Supply Requirement: Analog and Digital
• Output Type: Current
• Single Supply Voltage (min): 4.5V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / Rohs Status: Not Compliant

FUNCTIONAL DESCRIPTION
Figure 16 shows a simplified block diagram of the AD9754. The
AD9754 consists of a large PMOS current source array that is
capable of providing up to 20 mA of total current. The array
is divided into 31 equal currents that make up the five most
significant bits (MSBs). The next four bits or middle bits consist
of 15 equal current sources whose value is 1/16th of an MSB
current source. The remaining LSBs are binary weighted frac-
tions of the middle bits current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances its dynamic performance for multitone or low
amplitude signals and helps maintain the DAC’s high output
impedance (i.e., >100 k ).
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on a new
architecture that drastically improves distortion performance.
This new switch architecture reduces various timing errors and
provides matching complementary drive signals to the inputs of
the differential current switches.
The analog and digital sections of the AD9754 have separate
power supply inputs (i.e., AVDD and DVDD). The digital sec-
tion, which is capable of operating up to a 125 MSPS clock rate
and over +2.7 V to +5.5 V operating range, consists of edge-
triggered latches and segment decoding logic circuitry. The
analog section, which can operate over a +4.5 V to +5.5 V range
includes the PMOS current sources, the associated differential
switches, a 1.20 V bandgap voltage reference and a reference
control amplifier.
The full-scale output current is regulated by the reference con-
trol amplifier and can be set from 2 mA to 20 mA via an exter-
nal resistor, R
both the reference control amplifier and voltage reference V
sets the reference current I
segmented current sources with the proper scaling factor. The
full-scale current, I
REV. A
SET
0.1 F
. The external resistor, in combination with
OUTFS
CLOCK
, is 32 times the value of I
V
REFIO
R
2k
SET
REF
, which is mirrored over to the
+5V
I
REF
REFIO
FS ADJ
DVDD
DCOM
CLOCK
SLEEP
+1.20V REF
Figure 16. Functional Block Diagram
REFLO
REF
SEGMENTED SWITCHES
.
FOR DB13–DB5
DIGITAL DATA INPUTS (DB13–DB0)
150pF
REFIO
,
LATCHES
CURRENT SOURCE
–9–
ARRAY
DAC TRANSFER FUNCTION
The AD9754 provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current out-
put, I
while IOUTB, the complementary output, provides no current.
The current output appearing at IOUTA and IOUTB is a func-
tion of both the input code and I
where DAC CODE = 0 to 16383 (i.e., Decimal Representation).
As mentioned previously, I
current I
and external resistor R
where I
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, R
that R
IOUTA or IOUTB as would be the case in a doubly terminated
50
at the IOUTA and IOUTB nodes is simply:
Note that the full-scale value of V
exceed the specified output compliance range to maintain speci-
fied distortion and linearity performance.
The differential voltage, V
IOUTB is:
Substituting the values of IOUTA, IOUTB and I
be expressed as:
PMOS
+5V
SWITCHES
V
V
AVDD
OUTA
OUTB
IOUTA = (DAC CODE/16384)
IOUTB = (16383 – DAC CODE)/16384
I
V
V
V
LSB
OUTFS
OUTFS
or 75
DIFF
DIFF
DIFF
LOAD
REF
LOAD
REF
AD9754
= IOUTA R
= IOUTB
= (IOUTA – IOUTB)
= {(2 DAC CODE – 16383)/16384}
=
, when all bits are high (i.e., DAC CODE = 16383)
= V
, which is nominally set by a reference voltage V
= 32
may represent the equivalent load resistance seen by
ACOM
, that are tied to analog common, ACOM. Note
{(32 R
cable. The single-ended voltage output appearing
ICOMP
IOUTB
REFIO
IOUTA
I
REF
LOAD
/R
R
0.1 F
SET
SET
I
LOAD
LOAD
OUTB
/R
. It can be expressed as:
DIFF
SET
OUTFS
I
OUTA
)
, appearing across IOUTA and
V
DIFF
OUTFS
V
V
R
50
is a function of the reference
OUTA
OUTB
LOAD
REFIO
R
= V
LOAD
OUTA
I
and can be expressed as:
and V
OUTFS
– V
V
R
50
OUTA
OUTB
LOAD
OUTB
I
AD9754
OUTFS
REF
should not
; V
DIFF
REFIO
can
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)