AD9754ARU Analog Devices Inc, AD9754ARU Datasheet - Page 17

• Manufacturer Part Number: AD9754ARU
• Description: IC DAC 14BIT 125MSPS 28-TSSOP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9754ARU

• Mounting Type: Surface Mount
• Rohs Status: RoHS non-compliant
• Settling Time: 35ns
• Number Of Bits: 14
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 220mW
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• Resolution (bits): 14bit
• No. Of Pins: 28
• Update Rate: 125MSPS
• Peak Reflow Compatible (260 C): No
• No. Of Bits: 14 Bit
• Leaded Process Compatible: No
• Voltage Rating: 5V
• Number Of Channels: 1
• Resolution: 14b
• Interface Type: Parallel
• Single Supply Voltage (typ): 5V
• Dual Supply Voltage (typ): Not RequiredV
• Power Supply Requirement: Analog and Digital
• Output Type: Current
• Single Supply Voltage (min): 4.5V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / Rohs Status: Not Compliant

f
ratio of 13.5 dB compared to a sine waves peak-to-rms ratio of
3 dB. A “snapshot” of this reconstructed multitone vector in the
time domain as shown in Figure 34b reveals the higher signal
content around the midscale value. As a result, a DAC’s “small-
scale” dynamic and static linearity becomes increasingly criti-
cal in obtaining low intermodulation distortion and maintaining
sufficient carrier-to-noise ratios for a given modulation scheme.
A DAC’s small-scale linearity performance is also an important
consideration in applications where additive dynamic range is
required for gain control purposes or “predistortion” signal
conditioning. For instance, a DAC with sufficient dynamic
range can be used to provide additional gain control of its
reconstructed signal. In fact, the gain can be controlled in
6 dB increments by simply performing a shift left or right on the
DAC’s digital input word. Other applications may intentionally
predistort a DAC’s digital input signal to compensate for
nonlinearities associated with the subsequent analog compo-
nents in the signal chain. For example, the signal compression
associated with a power amplifier can be compensated for by
predistorting the DAC’s digital input with the inverse nonlinear
transfer function of the power amplifier. In either case, the
DAC’s performance at reduced signal levels should be carefully
evaluated.
A full-scale single tone will induce all of the dynamic and static
nonlinearities present in a DAC that contribute to its distortion
and hence SFDR performance. Referring to Figure 3, as the
frequency of this reconstructed full-scale, single-tone waveform
increases, the dynamic nonlinearities of any DAC (i.e., AD9754)
tend to dominate thus contributing to the roll-off in its SFDR
performance. However, unlike most DACs, which employ an R-2R
ladder for the lower bit current segmentation, the AD9754 (as
REV. A
CLOCK
Figure 34b. Time Domain “Snapshot” of the Multitone
Waveform
/4). This particular multitone vector, has a peak-to-rms
–0.2000
–0.4000
–0.6000
–0.8000
–1.0000
1.0000
0.8000
0.6000
0.4000
0.2000
0.0000
TIME
–17–
well as other TxDAC members) exhibits an improvement in
distortion performance as the amplitude of a single tone is re-
duced from its full-scale level. This improvement in distortion
performance at reduced signal levels is evident if one compares
the SFDR performance vs. frequency at different amplitudes
(i.e., 0 dBFS, –6 dBFS and –12 dBFS) and sample rates as
shown in Figures 4 through 7. Maintaining decent “small-scale”
linearity across the full span of a DAC transfer function is also
critical in maintaining excellent multitone performance.
Although characterizing a DAC’s multitone performance tends
to be application-specific, much insight into the potential perfor-
mance of a DAC can also be gained by evaluating the DAC’s
swept power (i.e., amplitude) performance for single, dual and
multitone test vectors at different clock rates and carrier frequen-
cies. The DAC is evaluated at different clock rates when recon-
structing a specific waveform whose amplitude is decreased in
3 dB increments from full-scale (i.e., 0 dBFS). For each specific
waveform, a graph showing the SFDR (over Nyquist) perfor-
mance vs. amplitude can be generated at the different tested
clock rates as shown in Figures 9–11. Note that the carrier(s)-to-
clock ratio remains constant in each figure. In each case, an
improvement in SFDR performance is seen as the amplitude is
reduced from 0 dBFS to approximately –9.0 dBFS.
A multitone test vector may consist of several equal amplitude,
spaced carriers each representative of a channel within a defined
bandwidth as shown in Figure 37a. In many cases, one or more
tones are removed so the intermodulation distortion performance
of the DAC can be evaluated. Nonlinearities associated with the
DAC will create spurious tones of which some may fall back into
the “empty” channel thus limiting a channel’s carrier-to-noise
ratio. Other spurious components falling outside the band of
interest may also be important, depending on the system’s spectral
mask and filtering requirements.
This particular test vector was centered around one-half the
Nyquist bandwidth (i.e., f
Centering the tones at a much lower region (i.e., f
would lead to an improvement in performance while centering
the tones at a higher region (i.e., f
degradation in performance.
CLOCK
/4) with a passband of f
CLOCK
/2.5) would result in a
AD9754
CLOCK
CLOCK
/10)
/16.