DAC1405D650HW/C1,5 NXP Semiconductors, DAC1405D650HW/C1,5 Datasheet
DAC1405D650HW/C1,5
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DAC1405D650 Dual 14-bit DAC 650 Msps; 2×, 4× and 8× interpolating Rev. 3 — 10 September 2010 1. General description The DAC1405D650 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC) with selectable 2×, 4× or 8× interpolating ...
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... NXP Semiconductors 3. Applications Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA Communication: LMDS/MMDS, point-to-point Direct Digital Synthesis (DDS) Broadband wireless systems Digital radio links Instrumentation Automated Test Equipment (ATE) 4. Ordering information Table 1. Ordering information Type number Package Name DAC1405D650HW HTQFP100 DAC1405D650 Product data sheet Dual 14-bit DAC 650 Msps ...
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Block diagram DAC1405D650 FIR1 LATCH I13 I 2 × dual port/ interleaved data modes FIR1 LATCH Q 2 × Q13 CLKP CLOCK GENERATOR/ PLL CLKN RESET_N Fig 1. Block diagram SDO SCS_N SDIO ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning 1 V DDA(3V3) AUXAP 2 AUXAN 3 AGND DDA(1V8 DDA(1V8) AGND 7 CLKP 8 CLKN 9 10 AGND 11 V DDA(1V8) d.n.c. 12 d.n.c. 13 TM1 14 15 TM0 16 V DD(IO)(3V3) GNDIO 17 I13 18 I12 19 20 I11 21 I10 Fig 2. Pin configuration DAC1405D650 Product data sheet Dual 14-bit DAC 650 Msps ...
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... NXP Semiconductors 6.2 Pin description Table 2. Symbol V DDA(3V3) AUXAP AUXAN AGND V DDA(1V8) V DDA(1V8) AGND CLKP CLKN AGND V DDA(1V8) d.n.c. d.n.c. TM1 TM0 V DD(IO)(3V3) GNDIO I13 I12 I11 I10 DDD(1V8) DGND DDD(1V8) DGND DDD(1V8) DGND TM2 DGND DAC1405D650 Product data sheet Dual 14-bit DAC 650 Msps ...
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... NXP Semiconductors Table 2. Symbol V DDD(1V8) Q13/SELIQ Q12 DGND V DDD(1V8) Q11 Q10 Q9 Q8 DGND V DDD(1V8 GNDIO V DD(IO)(3V3) TM3 SDO SDIO SCLK SCS_N RESET_N d.n.c. VIRES GAPOUT V DDA(1V8) V DDA(1V8) AGND AUXBN AUXBP V DDA(3V3) AGND V DDA(1V8) AGND V DDA(1V8) AGND DAC1405D650 Product data sheet Dual 14-bit DAC 650 Msps ...
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... NXP Semiconductors Table 2. Symbol V DDA(1V8) AGND V DDA(1V8) AGND IOUTBN IOUTBP AGND n.c. AGND IOUTAP IOUTAN AGND V DDA(1V8) AGND V DDA(1V8) AGND V DDA(1V8) AGND V DDA(1V8) AGND AGND [ power supply G = ground I = input O = output. [ heatsink (exposed die pad to be soldered) DAC1405D650 Product data sheet Dual 14-bit DAC 650 Msps; 2×, 4× and 8× interpolating Pin description … ...
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... NXP Semiconductors 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V input/output supply voltage (3.3 V) DD(IO)(3V3) V analog supply voltage (3.3 V) DDA(3V3) V analog supply voltage (1.8 V) DDA(1V8) V digital supply voltage (1.8 V) DDD(1V8) V input voltage ...
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... NXP Semiconductors 9. Characteristics Table 5. Characteristics 1 DDA(1V8) DDD(1V8) DDA(3V3) ° +85 C; typical values measured at T specified. Symbol Parameter V input/output supply DD(IO)(3V3) voltage (3 analog supply voltage DDA(3V3) (3 analog supply voltage DDA(1V8) (1 digital supply voltage DDD(1V8) (1 input/output supply DD(IO)(3V3) current (3 analog supply current DDA(3V3) (3 ...
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... NXP Semiconductors Table 5. Characteristics …continued 1 DDA(1V8) DDD(1V8) DDA(3V3) ° +85 C; typical values measured at T specified. Symbol Parameter Clock inputs (CLKP and CLKN) V input voltage i V input differential idth threshold voltage R input resistance i C input capacitance i Digital inputs (I0 to I13 Q13) V LOW-level input voltage ...
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... NXP Semiconductors Table 5. Characteristics …continued 1 DDA(1V8) DDD(1V8) DDA(3V3) ° +85 C; typical values measured at T specified. Symbol Parameter Analog auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN) I auxiliary output current O(aux) V auxiliary output voltage compliance range O(aux) N auxiliary DAC DAC(aux)mono monotonicity Input timing (see ...
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... NXP Semiconductors Table 5. Characteristics …continued 1 DDA(1V8) DDD(1V8) DDA(3V3) ° +85 C; typical values measured at T specified. Symbol Parameter IMD3 third-order intermodulation distortion ACPR adjacent channel power ratio NSD noise spectral density [ guaranteed by design guaranteed by characterization 100 % industrially tested. CLKP and CLKN inputs are at differential LVDS levels. An external differential resistor with a value of between 80 Ω and 120 Ω should ...
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... NXP Semiconductors 10. Application information 10.1 General description The DAC1405D650 is a dual 14-bit DAC operating 650 Msps. Each DAC consists of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 8-bit binary weighted sub-DAC. With an input data rate 160 MHz, and a maximum output sampling rate of 650 Msps, the DAC1405D650 allows more flexibility for wide bandwidth and multi-carrier systems ...
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... NXP Semiconductors RESET_N SCS_N SCLK SDIO R SDO (optional) R/W indicates the mode access, (see Fig 3. SPI protocol Table 6. R Table 7 byte. Table A[4:0]: indicates which register is being addressed. In the case of a multiple transfer, this address concerns the first register after which the next registers follow directly in a decreasing order according to 10 ...
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... NXP Semiconductors RESET_N SCS_N Fig 4. The SPI timing characteristics are given in Table 8. Symbol f SCLK t w(SCLK) t su(SCS_N) t h(SCS_N) t su(SDIO) t h(SDIO) t w(RESET_N) 10.2.3 Detailed descriptions of registers An overview of the details for all registers is provided in DAC1405D650 Product data sheet Dual 14-bit DAC 650 Msps; 2×, 4× and 8× interpolating ...
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Table 9. Register allocation map Address Register name R/W Bit definition b7 0 00h COMMon R/W 3W_SPI 1 01h TXCFG R/W NCO_ON 2 02h PLLCFG R/W PLL_PD 3 03h FREQNCO_LSB R/W 4 04h FREQNCO_LISB R/W 5 05h FREQNCO_UISB R/W 6 ...
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... NXP Semiconductors 10.2.4 Registers detailed description Please refer to tables, all the values emphasized in bold are the default values. Table 10. Default settings are shown highlighted. Bit Table 11. Default settings are shown highlighted. Bit Symbol 7 NCO_ON 6 NCO_LP_SEL 5 INV_SIN_SEL DAC1405D650 Product data sheet Dual 14-bit DAC 650 Msps; 2×, 4× and 8× interpolating Table 9 for a register overview and their default values ...
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... NXP Semiconductors Table 11. Default settings are shown highlighted. Bit Symbol MODULATION[2:0] R INTERPOLATION[1 :0] Table 12. Default settings are shown highlighted. Bit PLL_DIV[1: PLL_PHASE[1:0] 0 Table 13. Bit FREQ_NCO[7:0] DAC1405D650 Product data sheet Dual 14-bit DAC 650 Msps; 2×, 4× and 8× interpolating TXCFG register (address 01h) bit description ...
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... NXP Semiconductors Table 14. Bit FREQ_NCO[15:8] Table 15. Bit FREQ_NCO[23:16] Table 16. Bit FREQ_NCO[31:24] Table 17. Bit PH_NCO[7:0] Table 18. Bit PH_NCO[15:8] Table 19. Default settings are shown highlighted. Bit DAC_A_OFFSET[5:0] Table 20. Bit DAC_A_GAIN_COARSE[1 DAC_A_GAIN_FINE[5:0] DAC1405D650 Product data sheet Dual 14-bit DAC 650 Msps; 2×, 4× and 8× interpolating ...
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... NXP Semiconductors Table 21. Bit DAC_A_GAIN_COARSE[3 DAC_A_OFFSET[11:6] DAC1405D650 Product data sheet Dual 14-bit DAC 650 Msps; 2×, 4× and 8× interpolating DAC_A_Cfg_3 register (address 0Bh) bit description Symbol Access Value R/W ] R/W All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 September 2010 ...
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... NXP Semiconductors Table 22. Default settings are shown highlighted. Bit DAC_B_OFFSET[5:0] Table 23. Bit DAC_B_GAIN_COARSE[1 DAC_B_GAIN_FINE[5:0] Table 24. Bit DAC_B_GAIN_COARSE[3 DAC_B_OFFSET[11:6] Table 25. Default settings are shown highlighted. Bit 1 0 Table 26. Bit Table 27. Default settings are shown highlighted. Bit DAC1405D650 Product data sheet Dual 14-bit DAC 650 Msps; 2×, 4× and 8× interpolating ...
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... NXP Semiconductors Table 28. Bit Table 29. Default settings are shown highlighted. Bit 10.3 Input data The setting applied to MODE_SEL (register 00h[3]; see defines whether the DAC1405D650 operates in the Dual-port mode or in the Interleaved mode (see Table 30. Bit 3 setting 0 1 10.3.1 Dual-port mode The data input for Dual-port mode operation is shown in DAC has its own independent data input ...
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... NXP Semiconductors Fig 6. In the Interleaved mode, both DACs use the same data input at twice the Dual-port mode frequency. Data enters the latch on the rising edge of the internal clock signal. The data is sent to either latch I or latch Q, depending on the SELIQ signal. ...
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... NXP Semiconductors 10.4 Input clock The DAC1405D650 can operate with a clock frequency of 160 MHz in the Dual-port mode and up to 320 MHz in the Interleaved mode. The input clock is LVDS (see can also be interfaced with CML (see Fig 8. Fig 9. DAC1405D650 Product data sheet Dual 14-bit DAC 650 Msps ...
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... NXP Semiconductors 10.5 Timing The DAC1405D650 can operate at an update rate (f data rate (f diagram”. (CLKP-CLKN) Fig 10. Input timing diagram The typical performances are measured duty cycle but any timing within the limits of the characteristics will not alter the performance. In Table 31 The setting applied to PLL_DIV[1:0] (register 02h[4:3] ...
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... NXP Semiconductors 10.6 FIR filters The DAC1405D650 integrates three selectable Finite Impulse Response (FIR) filters which allows the device to use 2×, 4× or 8× interpolation rates. All three interpolation filters have a stop-band attenuation of at least 80 dBc and a pass-band ripple of less than 0.0005 dB. ...
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... NXP Semiconductors 10.7 Quadrature modulator and Numerically Controlled Oscillator (NCO) The quadrature modulator allows the 14-bit I and Q data to be mixed with the carrier signal generated by the NCO. The frequency of the NCO is programmed over 32-bit and allows the sign of the sine component to be inverted in order to operate positive or negative, lower or upper single sideband up-conversion ...
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... NXP Semiconductors Table 34. First interpolation filter Lower H(1) H(2) H(3) H(4) H(5) 10.9 DAC transfer function The full-scale output current for each DAC is the sum of the two complementary current outputs The output current depends on the digital input data: I IOUTP I IOUTN The setting applied to CODING (register 00h[2]; see defines whether the DAC1405D650 operates with a binary input or a two’ ...
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... NXP Semiconductors The reference current is generated via an external resistor of 910 Ω connected to pin VIRES. A control amplifier sets the appropriate full-scale current (I (see Figure 11 “Internal reference Fig 11. Internal reference configuration This configuration is optimum for temperature drift compensation because the bandgap reference voltage can be matched to the voltage across the feedback resistor. ...
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... NXP Semiconductors Table 36. Default settings are shown highlighted. DAC_GAIN_COARSE[3:0] Decimal The settings applied to DAC_A_GAIN_FINE[5:0] (register 0Ah; see “DAC_A_Cfg_2 register (address 0Ah) bit (register 0Dh; see the fine variation of the full-scale current (see Table 37. Default settings are shown highlighted. DAC_GAIN_FINE[5:0] Decimal −32 ...
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... NXP Semiconductors Table 38. Default settings are shown highlighted. DAC_OFFSET[11:0] Decimal −2048 −2047 ... − ... 2046 2047 10.12 Analog output The DAC1405D650 has two output channels each of which produces two complementary current outputs. These allow the even-order harmonics and noise to be reduced. The pins ...
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... NXP Semiconductors 10.13 Auxiliary DACs The DAC1405D650 integrates 2 auxiliary DACs that can be used to compensate for any offset between the DAC and the next stage in the transmission path. Both auxiliary DACs have a resolution of 10-bit and are current sources (referenced to ground AUX The output current depends on the auxiliary DAC data: ...
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... NXP Semiconductors 10.14 Output configuration 10.14.1 Basic output configuration The use of a differentially-coupled transformer output provides optimum distortion performance (see helps to match the impedance and provides electrical isolation. Fig 13 The DAC1405D650 can operate recommended to connect the center tap of the transformer Ω resistor connected to the 3 ...
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... NXP Semiconductors Fig 15. An example interface to a 1.7 V Figure 16 input level. Fig 16. An example interface to a 3.3 V The auxiliary DACs can be used to control the offset in a precise range or with precise steps. Figure 17 a 1.7 V DAC1405D650 Product data sheet Dual 14-bit DAC 650 Msps; 2×, 4× and 8× interpolating ...
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... NXP Semiconductors Fig 17. An example interface to a 1.7 V Figure 18 a 3.3 V Fig 18. An example interface to a 3.3 V The constraints to adjust the interface are the output compliance range of the DAC and the auxiliary DACs, the input common mode level of the AQM, and the range of offset correction ...
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... NXP Semiconductors 10.14.3 AC interface to an Analog Quadrature Modulator (AQM) When the AQM common mode voltage is close to ground, the DAC1405D650 must be AC-coupled and the auxiliary DACs are needed for offset correction. Figure 19 input level when using auxiliary DACs. Fig 19. An example interface to a 0.5 V ...
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... NXP Semiconductors 10.15 Power and grounding In order to obtain optimum performance recommended that the 1.8 V analog power supplies on pins 5, 11, 71, 77 and 99 should not be connected with the ones on pins 6, 70, 79, 81, 83, 93, 95 and 97 on the top layer. To optimize the decoupling, the power supplies should be decoupled with the following ground pins: • ...
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... NXP Semiconductors 10.16 Alternative parts The following alternative parts are available. Table 40. Type number DAC1005D650 DAC1205D650 DAC1405D650 Product data sheet Dual 14-bit DAC 650 Msps; 2×, 4× and 8× interpolating Alternative parts Description dual 10-bit DAC dual 12-bit DAC All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 11. Package outline HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads; body mm; exposed die pad y exposed die pad side pin 1 index 100 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.05 0.27 mm 1.2 0.25 0.05 0.95 0.17 Note 1 ...
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... NXP Semiconductors 12. Abbreviations Table 41. Acronym BW CDMA CML CMOS DAC FIR GSM IF IMD3 LISB LMDS LSB LTE LVDS MMDS MSB NCO NMOS PLL SFDR SPI TD-SCDMA UISB WCDMA WiMAX DAC1405D650 Product data sheet Dual 14-bit DAC 650 Msps; 2×, 4× and 8× interpolating ...
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... NXP Semiconductors 13. Glossary Spurious-Free Dynamic Range (SFDR): — The ratio between the RMS value of the reconstructed output sine wave and the RMS value of the largest spurious observed (harmonic and non-harmonic, excluding DC component) in the frequency domain. Intermodulation Distortion (IMD): — From a dual-tone digital input sine wave (these two frequencies being close together), the intermodulation distortion products IMD2 and IMD3 (respectively, second and third-order components) are defined below ...
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... NXP Semiconductors 14. Revision history Table 42. Revision history Document ID Release date DAC1405D650 v.3 20100910 • Modifications: Figure DAC1405D650 v.2 20100708 • Modifications: Figure 1: changed demodulator to modulator • Table 5: changed DAC Q to DAC • Table 5: removed note 4 • Section 10.2.1: changed “ bytes” to “ bytes” in third paragraph • ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... Dual 14-bit DAC 650 Msps; 2×, 4× and 8× interpolating NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Thermal characteristics . . . . . . . . . . . . . . . . . . 8 9 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 10 Application information 10.1 General description . . . . . . . . . . . . . . . . . . . . 13 10.2 Serial interface (SPI ...