DAC1405D650HW/C1,5 NXP Semiconductors, DAC1405D650HW/C1,5 Datasheet - Page 10

• Manufacturer Part Number: DAC1405D650HW/C1,5
• Description: IC DAC 14BIT 650MSPD DL 100HTQFP
• Manufacturer: NXP Semiconductors

Specifications of DAC1405D650HW/C1,5

• Settling Time: 20ns
• Number Of Bits: 14
• Data Interface: SPI™
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 1.4W
• Operating Temperature: -45°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286775518

NXP Semiconductors
Table 5.
V
+85
specified.
DAC1405D650
Product data sheet
Symbol
Clock inputs (CLKP and CLKN)
V
V
R
C
Digital inputs (I0 to I13, Q0 to Q13)
V
V
I
I
Digital inputs (SDO, SDIO, SCLK, SCS_N and RESET_N)
V
V
I
I
Analog outputs (IOUTAP, IOUTAN, IOUTBP and IOUTBN)
I
V
R
C
N
ΔE
ΔE
Reference voltage output (GAPOUT)
V
ΔV
I
IL
IH
IL
IH
O(fs)
O(ref)
DDA(1V8)
i
idth
IL
IH
IL
IH
O
O(ref)
i
i
o
o
DAC(mono)
O
G
O(ref)
°
C; typical values measured at T
= V
Characteristics
DDD(1V8)
Parameter
input voltage
input differential
threshold voltage
input resistance
input capacitance
LOW-level input voltage
HIGH-level input
voltage
LOW-level input current V
HIGH-level input
current
LOW-level input voltage
HIGH-level input
voltage
LOW-level input current V
HIGH-level input
current
full-scale output current register value = 00h
output voltage
output resistance
output capacitance
DAC monotonicity
offset error variation
gain error variation
reference output
voltage
reference output
voltage variation
reference output
current
= 1.8 V; V
…continued
DDA(3V3)
[2]
amb
= V
= 25
Conditions
CLKP; or CLKN |V
|V
V
V
default register
compliance range
guaranteed
T
external voltage 1.25 V
All information provided in this document is subject to legal disclaimers.
amb
IL
IH
IL
IH
gpd
DD(IO)(3V3)
= 1.0 V
= 1.0 V
= 2.3 V
= 2.3 V
| < 50 mV
°
= 25 °C
C; R
Rev. 3 — 10 September 2010
L
Dual 14-bit DAC, up to 650 Msps; 2×, 4× and 8× interpolating
= 50
= 3.3 V; AGND, DGND and GNDIO shorted together; T
Ω
gpd
; I
O(fs)
| < 50 mV
= 20 mA; maximum sample rate; PLL on unless otherwise
D
C
C
C
D
C
Test
[1]
C
C
D
C
I
I
C
I
I
C
C
D
D
C
I
C
D
[3]
[3]
Min
825
−100
-
-
GNDIO -
2.3
-
-
GNDIO -
2.3
-
-
-
1.8
-
-
-
-
1.2
-
-
-
-
DAC1405D650
Typ
-
-
10
0.5
-
60
80
-
20
20
1.6
20
-
250
3
8
6
18
1.25
117
40
Max
1575
+100
-
-
1.0
V
-
-
1.0
V
-
-
-
-
V
-
-
-
-
-
1.29
-
-
© NXP B.V. 2010. All rights reserved.
DD(IO)(3V3)
DD(IO)(3V3)
DDA(3V3)
amb
=
−
Unit
mV
mV
MΩ
pF
V
V
μA
μA
V
V
nA
nA
mA
mA
V
kΩ
pF
bit
ppm/°C
ppm/°C
V
ppm/°C
μA
40
10 of 45
°
C to