MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 26

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Figure 11: Array Organization – MT29F4G16 (x16)
Table 7: Array Addressing – MT29F4G16 (x16)
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Second
Fourth
Cycle
Third
Fifth
First
Cache Register
Data Register
2048 blocks
4096 blocks
per device
per plane
I/O[15:8]
LOW
LOW
LOW
LOW
LOW
Notes:
(0, 2, 4, 6, ..., 4092, 4094)
even-numbered blocks
BA15
LOW
LOW
I/07
CA7
BA7
Plane of
1. Block address concatenated with page address = actual page address. CAx = column ad-
2. If CA10 = 1, then CA[9:5] must be 0.
3. BA6 controls plane selection.
1024
1024
1 block
dress; PAx = page address; BAx = block address.
1056 words
BA14
LOW
LOW
I/06
CA6
BA6
32
32
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
(1, 3, 5, 7, ..., 4093, 4095)
odd-numbered blocks
BA13
LOW
LOW
I/05
CA5
PA5
1024
1024
1 block
Plane of
1056 words
26
BA12
LOW
LOW
I/04
CA4
PA4
32
32
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1 page
1 block
1 plane
1 device
BA11
Device and Array Organization
LOW
LOW
I/03
CA3
PA3
DQ0
DQ15
= (1K + 32 words)
= (1K + 32) words x 64 pages
= (64K + 2K) words
= (64K + 2K) words x 2048 blocks
= 2112Mb
= 2112Mb x 2 planes
= 4224Mb
CA10
BA10
LOW
CA2
I/02
PA2
© 2009 Micron Technology, Inc. All rights reserved.
BA17
CA1
CA9
BA9
I/01
PA1
BA16
CA0
CA8
BA8
I/00
PA0