MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 33

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Asynchronous Data Output
Figure 17: Asynchronous Data Output Cycles
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
RDY
I/Ox
CE#
RE#
Data can be output from a die (LUN) if it is in a READY state. Data output is supported
following a READ operation from the NAND Flash array. Data is output from the cache
register of the selected die (LUN) to I/O[7:0] on the falling edge of RE# when CE# is
LOW, ALE is LOW, CLE is LOW, and WE# is HIGH.
If the host controller is using a
rising edge of RE# (see the figure below for proper timing). If the host controller is using
a
Using the READ STATUS ENHANCED (78h) command prevents data contention follow-
ing an interleaved die (multi-LUN) operation. After issuing the READ STATUS EN-
HANCED (78h) command, to enable data output, issue the READ MODE (00h) command.
Data output requests are typically ignored by a die (LUN) that is busy (RDY = 0); howev-
er, it is possible to output data from the status register even when a die (LUN) is busy by
first issuing the READ STATUS or READ STATUS ENHANCED (78h) command.
t CEA
t RR
t
RC of less than 30ns, the host can latch the data on the next falling edge of RE#.
t REA
t RP
D
OUT
t RC
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
t REH
t REA
33
t
RC of 30ns or greater, the host can latch the data on the
Asynchronous Interface Bus Operation
D
OUT
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t RHZ
t REA
D
t COH
© 2009 Micron Technology, Inc. All rights reserved.
OUT
t RHOH
t RHZ
t CHZ
Don’t Care