MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 65

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Read Operations
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
The READ PAGE (00h-30h) command, when issued by itself, reads one page from the
NAND Flash array to its cache register and enables data output for that cache register.
During data output the following commands can be used to read and modify the data
in the cache registers: RANDOM DATA READ (05h-E0h) and RANDOM DATA INPUT
(85h).
Read Cache Operations
To increase data throughput, the READ PAGE CACHE series (31h, 00h-31h) commands
can be used to output data from the cache register while concurrently copying a page
from the NAND Flash array to the data register.
To begin a read page cache sequence, begin by reading a page from the NAND Flash
array to its corresponding cache register using the READ PAGE (00h-30h) command.
R/B# goes LOW during
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• READ PAGE CACHE SEQUENTIAL (31h) – copies the next sequential page from the
• READ PAGE CACHE RANDOM (00h-31h) – copies the page specified in this command
After the READ PAGE CACHE series (31h, 00h-31h) command has been issued, R/B#
goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for
the next page begins copying data from the array to the data register. After
R/B# goes HIGH and the die’s (LUN’s) status register bits indicate the device is busy
with a cache operation (RDY = 1, ARDY = 0). The cache register becomes available and
the page requested in the READ PAGE CACHE operation is transferred to the data regis-
ter. At this point, data can be output from the cache register, beginning at column
address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the
column address of the data output by the die (LUN).
After outputting the desired number of bytes from the cache register, either an addition-
al READ PAGE CACHE series (31h, 00h-31h) operation can be started or the READ PAGE
CACHE LAST (3Fh) command can be issued.
If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the tar-
get, and RDY = 0 and ARDY = 0 on the die (LUN) for
copied into the cache register. After
ARDY = 1, indicating that the cache register is available and that the die (LUN) is ready.
Data can then be output from the cache register, beginning at column address 0. The
RANDOM DATA READ (05h-E0h) command can be used to change the column address
of the data being output.
For READ PAGE CACHE series (31h, 00h-31h, 3Fh), during the die (LUN) busy time,
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(70h, 78h) and RESET (FFh). When RDY = 1 and ARDY = 0, the only valid commands
during READ PAGE CACHE series (31h, 00h-31h) operations are status operations (70h,
78h), READ MODE (00h), READ PAGE CACHE series (31h, 00h-31h), RANDOM DATA
READ (05h-E0h), and RESET (FFh).
R (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of these commands:
RCBSY, when RDY = 0 and ARDY = 0, the only valid commands are status operations
NAND Flash array to the data register
from the NAND Flash array to its corresponding data register
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
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R and the selected die (LUN) is busy (RDY = 0, ARDY = 0). After
65
t
RCBSY, R/B# goes HIGH and RDY = 1 and
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RCBSY while the data register is
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Read Operations
t
RCBSY while
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RCBSY,