MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 57

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Status Operations
Table 21: Status Register Definition
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Bit
SR
7
6
5
4
3
2
1
0
Write protect
FAILC (N - 1)
Program
ARDY
Page
RDY
FAIL
–
–
–
Notes:
Program Page
Cache Mode
Write protect
FAILC (N - 1)
RDY
Each die (LUN) provides its status independently of other die (LUNs) on the same tar-
get through its 8-bit status register.
After the READ STATUS (70h) or READ STATUS ENHANCED (78h) command is issued,
status register output is enabled. The contents of the status register are returned on I/
O[7:0] for each data output request.
When the asynchronous interface is active and status register output is enabled,
changes in the status register are seen on I/O[7:0] as long as CE# and RE# are LOW; it is
not necessary to toggle RE# to see the status register update.
While monitoring the status register to determine when a data transfer from the Flash
array to the data register (
command to disable the status register and enable data output (see Read Operations).
The READ STATUS (70h) command returns the status of the most recently selected die
(LUN). To prevent data contention during or following an interleaved die (multi-LUN)
operation, the host must enable only one die (LUN) for status output by using the READ
STATUS ENHANCED (78h) command (see Interleaved Die (Multi-LUN) Operations).
With internal ECC enabled, a READ STATUS command is required after completion of
the data transfer (
FAIL (N)
ARDY
1. Status register bit 6 is 1 when the cache is ready to accept new data. R/B# follows bit 6.
2. Status register bit 5 is 0 during the actual programming operation. If cache mode is
3. A status register bit defined as Rewrite Recommended signifies that the page includes
4. A status register bit defined as FAIL signifies that an uncorrectable READ error has occur-
1
–
–
–
cache
used, this bit will be 1 when all internal operations are complete.
acertain number of READ errors per sector (512B (main) + 4B (spare) + 8B (parity). A re-
writeof this page is recommended. (Up to a 4-bit error has been corrected if internal
ECC was enabled.)
red.
2
recommended
Write protect
Page Read
Reserved
Rewrite
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
ARDY
t
FAIL
RDY
R_ECC) to determine whether an uncorrectable read error occurred.
–
–
4
t
R) is complete, the host must issue the READ MODE (00h)
3
57
Cache Mode
Write protect Write protect 0 = Protected
Page Read
RDY
ARDY
1
–
–
–
–
–
cache
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Block Erase
ARDY
RDY
FAIL
–
–
–
–
1 = Not protected
0 = Busy
1 = Ready
Don't Care
Don't Care
0 = Normal or uncorrectable
1 = Rewrite recommended
Don't Care
Don't Care
0 = Successful PROGRAM/
ERASE/READ
1 = Error in PROGRAM/
ERASE/READ
© 2009 Micron Technology, Inc. All rights reserved.
Status Operations
Description