MT41J256M8HX-15E IT:D Micron Technology Inc, MT41J256M8HX-15E IT:D Datasheet - Page 84

• Manufacturer Part Number: MT41J256M8HX-15E IT:D
• Description: MICMT41J256M8HX-15E_IT:D 2GB DDR3 SDRAM
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M8HX-15E IT:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: -40C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
Notes:
10. The clock’s
11. Spread spectrum is not included in the jitter specification values. However, the input
12. The clock’s
13. The period jitter (
14.
15.
16. The cycle-to-cycle jitter (
17. The cumulative jitter error (
18.
19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transi-
1. Parameters are applicable with 0°C ≤ T
2. All voltages are referenced to V
3. Output timings are only valid for R
4. The unit
5. AC timing and I
6. All timings that use time-based values (ns, µs, ms) should use
7. Strobe or DQSdiff refers to the DQS and DQS# differential crossing point when DQS is
8. This output load is used for all AC timing (except ODT reference timing) and slew rates.
9. When operating in DLL disable mode, Micron does not warrant compliance with normal
The unit CK represents one clock cycle of the input clock, counting the actual clock edges.
ment, but input timing is still referenced to V
DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum slew
rate for the input signals used to test the device is 1 V/ns for single-ended inputs and 2 V/
ns for differential inputs in the range between V
the correct number of clocks (Table 56 (page 78) uses CK or
In the case of noninteger results, all minimum limits are to be rounded up to the nearest
whole integer, and all maximum limits are to be rounded down to the nearest whole
integer.
the rising edge. Clock or CK refers to the CK and CK# differential crossing point when
CK is the rising edge.
The actual test load may be different. The output signal voltage reference point is V
2 for single-ended signals and the crossing point for differential signals (see Figure 30
(page 71)).
mode timings or functionality.
MIN is the smallest clock rate allowed, with the exception of a deviation due to clock
jitter. Input clock jitter is allowed provided it does not exceed values specified and must
be of a random Gaussian distribution in nature.
clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with
an additional 1% of
trum may not use a clock rate below
secutive clocks and is the smallest clock half period allowed, with the exception of a
deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed
values specified and must be of a random Gaussian distribution in nature.
or nominal clock. It is allowed in either the positive or negative direction.
t
ing edge to the following falling edge.
t
ing edge to the following rising edge.
to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL
locking time.
50, is the amount of clock time allowed to accumulate consecutively away from the aver-
age clock over n number of clock cycles.
t
differential DQS, DQS# slew rate.
tion edge to its respective data strobe signal (DQS, DQS#) crossing.
CH(ABS) is the absolute instantaneous clock high pulse width as measured from one ris-
CL(ABS) is the absolute instantaneous clock low pulse width as measured from one fall-
DS (base) and
t
CK (AVG) represents the actual
t
t
CK (AVG) is the average clock over any 200 consecutive clocks and
CH (AVG) and
t
DH (base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns
DD
t
JITper) is the maximum deviation in the clock period from the average
tests may use a V
t
CK(AVG) as a long-term jitter component; however, the spread spec-
t
JITcc) is the amount the clock period can deviate from one cycle
84
t
CL (AVG) are the average half clock period over any 200 con-
t
ERRnper), where n is the number of clocks between 2 and
SS
.
ON34
IL
Micron Technology, Inc. reserves the right to change products or specifications without notice.
-to-V
t
CK (AVG) MIN.
C
output buffer selection.
≤ +95°C and V
t
CK (AVG) of the input clock under operation.
IH
swing of up to 900mV in the test environ-
2Gb: x4, x8, x16 DDR3 SDRAM
REF
(except
IL(AC)
and V
DD
/V
t
IS,
DDQ
IH(AC)
t
t
CK [AVG] interchangeably).
IH,
© 2006 Micron Technology, Inc. All rights reserved.
t
CK (AVG) to determine
= +1.5V ±0.075V.
t
.
DS, and
t
DH use the AC/
t
CK(AVG)
DDQ
/