MT41J256M8HX-15E IT:D Micron Technology Inc, MT41J256M8HX-15E IT:D Datasheet - Page 95

• Manufacturer Part Number: MT41J256M8HX-15E IT:D
• Description: MICMT41J256M8HX-15E_IT:D 2GB DDR3 SDRAM
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M8HX-15E IT:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: -40C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
20. The setup and hold times are listed converting the base specification values (to which
21. When the device is operated with input clock jitter, this parameter needs to be derated
22. Single-ended signal parameter.
23. The DRAM output timing is aligned to the nominal or average clock. Most output param-
24. The maximum preamble is bound by
25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its
26. The
27. The maximum postamble is bound by
28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT com-
29.
30. These parameters are measured from a command/address signal transition edge to its
31. For these parameters, the DDR3 SDRAM device supports
32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the inter-
33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for
34. The start of the write recovery time is defined as follows:
35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in High-
36. The refresh period is 64ms when T
derating tables apply) to V
of 1 V/ns, are for reference only.
by the actual
deratings are relative to the SDRAM input clock).
eters must be derated by the actual jitter error when input clock jitter is present, even
when within specification. This results in each parameter becoming larger. The follow-
ing parameters are required to be derated by subtracting
(MIN),
quired to be derated by subtracting
(DQS) MAX,
subtracting
respective clock signal (CK, CK#) crossing. The specification values are not affected by
the amount of clock jitter applied, as these are relative to the clock signal crossing.
These parameters should be met whether clock jitter is present.
mands. In addition, after any change of latency
t
slew rate and 2 V/ns CK, CK# differential slew rate.
respective clock (CK, CK#) signal crossing. The specification values are not affected by
the amount of clock jitter applied as the setup and hold times are relative to the clock
signal crossing that latches the command/address. These parameters should be met
whether clock jitter is present.
[ns]/
ple, the device will support
cations are met. This means that for DDR3-800 6-6-6, of which
support
met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are
valid even if six clocks are less than 15ns due to input clock jitter.
nal PRECHARGE command until
• For BL8 (fixed by MRS and OTF): Rising clock edge four clock cycles after WL
• For BC4 (OTF): Rising clock edge four clock cycles after WL
• For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL
Z. Until RESET# is LOW, the outputs are at risk of driving and could result in excessive
current, depending on bus activity.
age refresh rate of 7.8125µs. However, nine REFRESH commands should be asserted at
least once every 70.3µs. When T
though JEDEC specifies
provided that the maximum refresh period is not violated.
IS (base) and
t
t
CK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For exam-
DQSCKdll_dis parameter begins CL + AL - 1 cycles after the READ command.
t
LZ (DQS) MIN,
t
nRP = RU(
t
t
JITper (MAX), while
LZ(DQ) MAX, and
t
t
JITper (larger of
IH (base) values are for a single-ended 1 V/ns control/command/address
t
RP/
t
LZ (DQ) MIN, and
t
CK[AVG]) = 6 as long as the input clock jitter specifications are
t
REFI as a MAX, Micron allows REFRESH commands to be burst
95
REF
t
nRP (nCK) = RU(
when the slew rate is 1 V/ns. These values, with a slew rate
t
t
JITper (MIN) or
AON (MAX). The parameter
C
t
t
RAS (MIN) has been satisfied.
is greater than +85
RPRE (MAX) is derated by subtracting
C
is less than or equal to 85°C. This equates to an aver-
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
ERR
t
LZDQS (MAX).
t
HZDQS (MAX).
t
10PER
AON (MIN). The following parameters are re-
t
2Gb: x4, x8, x16 DDR3 SDRAM
RP/
(MIN):
t
JITper (MAX) of the input clock (output
t
t
XPDLL, timing must be met.
CK[AVG]) if all input clock jitter specifi-
°
t
C, the refresh period is 32ms. Al-
DQSCK (MAX),
t
nPARAM (nCK) = RU(
t
ERR
t
© 2006 Micron Technology, Inc. All rights reserved.
RPRE (MIN) is derated by
10PER
t
RP = 5ns, the device will
(MAX):
t
HZ (MAX),
t
JITper (MIN).
t
DQSCK
t
PARAM
t
t
WR.
LZ