MT41J256M8HX-15E:D

Manufacturer Part NumberMT41J256M8HX-15E:D
DescriptionMICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
ManufacturerMicron Technology Inc
TypeDDR3 SDRAM
Series-
MT41J256M8HX-15E:D datasheets
 

Specifications of MT41J256M8HX-15E:D

Organization256Mx8Address Bus18b
Maximum Clock Rate1.333GHzOperating Supply Voltage (typ)1.5V
Package TypeFBGAOperating Temp Range0C to 95C
Operating Supply Voltage (max)1.575VOperating Supply Voltage (min)1.425V
Supply Current165mAPin Count78
MountingSurface MountOperating Temperature ClassificationCommercial
Format - MemoryRAMMemory TypeDDR3 SDRAM
Memory Size2G (256M x 8)Speed667MHz
InterfaceParallelVoltage - Supply1.425 V ~ 1.575 V
Operating Temperature0°C ~ 95°CPackage / Case78-TFBGA
Lead Free Status / RoHS StatusCompliant  
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DDR3 SDRAM
MT41J512M4 – 64 Meg x 4 x 8 Banks
MT41J256M8 – 32 Meg x 8 x 8 Banks
MT41J128M16 – 16 Meg x 16 x 8 Banks
Features
• V
= V
Q = +1.5V ±0.075V
DD
DD
• 1.5V center-terminated push/pull I/O
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• CAS (READ) latency (CL): 5, 6, 7, 8, 9, 10, or 11
• POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2
• CAS (WRITE) latency (CWL): 5, 6, 7, 8, based on
• Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• T
of 0°C to 95°C
C
– 64ms, 8,192 cycle refresh at 0°C to 85°C
– 32ms at 85°C to 95°C
• Clock frequency range of 300–800 MHz
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
Table 1:
Key Timing Parameters
Speed Grade
Data Rate (MT/s)
-125
1600
-125E
1600
-15
1333
-15E
1333
-187
1066
-187E
1066
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D1.fm - Rev G 2/09 EN
Products and specifications discussed herein are subject to change by Micron without notice.
2Gb: x4, x8, x16 DDR3 SDRAM
1
Options
• Configuration
– 512 Meg x 4
– 256 Meg x 8
– 128 Meg x 16
• FBGA package (Pb-free) - x4, x8
– 78-ball (9mm x 11.5mm) Rev. D, F
– 82-ball (12.5mm x 15.5mm) Rev. A
• FBGA package (Pb-free) - x16
– 96-ball (9mm x 14mm) Rev. D
• Timing - cycle time
t
CK
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.25ns @ CL = 10 (DDR3-1600)
– 1.5ns @ CL = 10 (DDR3-1333)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.87ns @ CL = 8 (DDR3-1066)
– 1.87ns @ CL = 7 (DDR3-1066)
• Operating temperature
– Commercial (0°C ≤ T
– Industrial (–40°C ≤ T
• Revision
Notes: 1. Not all options listed can be combined to
define an offered product. Use the Part Cata-
log Search on
offerings.
t
t
t
Target
RCD-
RP-CL
RCD (ns)
11-11-11
13.75
10-10-10
12.5
10-10-10
15
9-9-9
13.5
8-8-8
15
7-7-7
13.1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
Features
Marking
512M4
256M8
128M16
HX
JE
HA
-125
-125E
-15
-15E
-187
-187E
≤ 95°C)
None
C
≤ 95°C;
IT
C
:A/:D/:F
www.micron.com
for available
t
RP (ns)
CL (ns)
13.75
13.75
12.5
12.5
15
15
13.5
13.5
15
15
13.1
13.1
©2006 Micron Technology, Inc. All rights reserved.

MT41J256M8HX-15E:D Summary of contents

  • Page 1

    ... PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D1.fm - Rev G 2/09 EN Products and specifications discussed herein are subject to change by Micron without notice. 2Gb: x4, x8, x16 DDR3 SDRAM 1 Options • Configuration – 512 Meg x 4 – 256 Meg x 8 – 128 Meg x 16 • ...

  • Page 2

    ... Meg x 4 512M4 256 Meg x 8 256M8 128 Meg x 16 128M16 Rev. Mark www.micron.com for available offerings. 2 2Gb: x4, x8, x16 DDR3 SDRAM 256 Meg x 8 128 Meg Meg banks 8K 32K (A[14:0]) 16K (A[13:0]) 8 (BA[2:0]) 8 (BA[2:0]) 1K (A[9:0]) 1K (A[9:0 Speed Revision :A/:D/:F Revision ...

  • Page 3

    ... SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 DLL Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Input Clock Frequency Change 101 PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_TOC.fm - Rev G 2/09 EN 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 ©2006 Micron Technology, Inc. All rights reserved. Table of Contents ...

  • Page 4

    ... Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry 175 Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit 177 PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_TOC.fm - Rev G 2/09 EN 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 ©2006 Micron Technology, Inc. All rights reserved. ...

  • Page 5

    ... IH (Command and Address – Clock . VAC for DS (DQ – Strobe . (DQ – Strobe .90 t MRD 110 t MOD 111 Micron Technology, Inc., reserves the right to change products or specifications without notice. 5 2Gb: x4, x8, x16 DDR3 SDRAM List of Figures ©2006 Micron Technology, Inc. All rights reserved. ...

  • Page 6

    ... DDR3_LOF.fm - Rev G 2/ RRD (MIN) and RCD (MIN 130 t DQSQ and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 and 139 6 2Gb: x4, x8, x16 DDR3 SDRAM List of Figures Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...

  • Page 7

    ... Figure 120: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping 180 PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_LOF.fm - Rev G 2/09 EN 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 7 ©2006 Micron Technology, Inc. All rights reserved. ...

  • Page 8

    ... Measurements – Clock Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ET, and DVAC) for CK - CK# and DQS - DQS .48 Characteristics 1. . Characteristics 1.575V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics 1.425V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Gb: x4, x8, x16 DDR3 SDRAM List of Tables .36 DD Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...

  • Page 9

    ... IH – AC150/DC100-Based .80 t VAC Above for Valid Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS/ DH – AC175/DC100-Based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS/ DH – AC150/DC100-Based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (Below for Valid Transition . 2Gb: x4, x8, x16 DDR3 SDRAM List of Tables Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...

  • Page 10

    ... READ = RD, RDS4, RDS8 READ AP = RDAP, RDAPS4, RDAPS8 REF = REFRESH RESET = START RESET PROCEDURE SRE = Self refresh entry Micron Technology, Inc., reserves the right to change products or specifications without notice. 10 2Gb: x4, x8, x16 DDR3 SDRAM State Diagram refresh SRE SRX REF Refreshing PDE ...

  • Page 11

    ... WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble ...

  • Page 12

    ... Row addressing is denoted as A[n:0](2Gb [x16] and 2Gb [x4, x8]). PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 2Gb: x4, x8, x16 DDR3 SDRAM Functional Description Micron Technology, Inc., reserves the right to change products or specifications without notice. 12 ...

  • Page 13

    ... Functional Block Diagrams DDR3 SDRAM is a high-speed, CMOS dynamic random access memory internally configured as an 8-bank DRAM. Figure 3: 512 Meg x 4 Functional Block Diagram ODT ZQ RESET# RZQ ZQCL, ZQCS CKE Control A12 logic CK, CK# BC4 (burst chop) CS# RAS# OTF CAS# WE# ...

  • Page 14

    ... I/O gating 3 DM mask logic Bank control logic (128 x128) Column decoder Column- 7 address counter/ 3 latch Columns 0, 1, and 2 14 2Gb: x4, x8, x16 DDR3 SDRAM Functional Block Diagrams ODT control V Q NOM Column 0, 1, and 2 CK, CK# sw1 DLL READ FIFO 16 128 ...

  • Page 15

    ... NF, DQ6 DQS NF, DQ4 REF RAS# SS ODT V CAS CS# WE# V BA0 BA2 RESET# V A13 SS Micron Technology, Inc., reserves the right to change products or specifications without notice. 15 2Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions NF, NF/TDQS DM, DM/TDQS SS DD DQ1 DQ3 NF, DQ7 NF, DQ5 CK# V CKE DD ...

  • Page 16

    ... NF, DQ6 DQS NF, DQ4 REF RAS# SS ODT V CAS CS# WE# V BA0 BA2 RESET# A13 SS Micron Technology, Inc., reserves the right to change products or specifications without notice. 16 2Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions NF, NF/TDQS DM,DM/TDQS SS DD DQ1 DQ3 NF, DQ7 NF, DQ5 CK# V CKE ...

  • Page 17

    ... DQ6 LDQS DQ4 REF RAS# SS ODT V CAS CS# WE# V BA0 BA2 RESET# A13 SS Micron Technology, Inc., reserves the right to change products or specifications without notice. 17 2Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions DQ12 UDQS# DQ14 UDQS DQ10 DQ8 LDM DQ1 DQ3 ...

  • Page 18

    ... On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command ...

  • Page 19

    ... V – No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). – No function: When configured device, these balls are NF. When configured device, these balls are defined as TDQS#, DQ[7:4] ...

  • Page 20

    ... On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command ...

  • Page 21

    ... V – No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). – No function: When configured device, these balls are NF. When configured device, these balls are defined as TDQS#, DQ[7:4] ...

  • Page 22

    ... On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS, and NF/ TDQS# (when TDQS is enabled) for the x8 ...

  • Page 23

    ... V – No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). Micron Technology, Inc., reserves the right to change products or specifications without notice. 23 2Gb: x4, x8, x16 DDR3 SDRAM and DC LOW ≤ ...

  • Page 24

    ... PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 0.8 ±0.1 Ball 11.5 ±0. Micron Technology, Inc., reserves the right to change products or specifications without notice. 24 2Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Ball A1 ID 1.2 MAX 0.25 MIN ©2006 Micron Technology, Inc. All rights reserved. ...

  • Page 25

    ... PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 0.75 ±0.1 Ball ±0. Micron Technology, Inc., reserves the right to change products or specifications without notice. 25 2Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Ball A1 ID 1.2 MAX 0.25 MIN ©2006 Micron Technology, Inc. All rights reserved. ...

  • Page 26

    ... PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 0.8 ±0.1 Ball ±0. Micron Technology, Inc., reserves the right to change products or specifications without notice. 26 2Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Ball A1 ID 1.2 MAX 0.25 MIN ©2006 Micron Technology, Inc. All rights reserved. ...

  • Page 27

    ... Storage temperature STG Notes greater than 0.6 × MAX operating case temperature. T Figure 12 on page 28). 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T operation. Input/Output Capacitance Table 7: Input/Output Capacitance Note 1 applies to the entire table Capacitance Parameters CK and CK# Δ ...

  • Page 28

    ... Operating case temperature Junction-to-case (TOP) Notes: 1. MAX operating case temperature. T Figure 12 thermal solution must be designed to ensure the DRAM device does not exceed the maxi- mum T 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T operation interval refresh rate. The use of SRT or ASR (if available) must be enabled. ...

  • Page 29

    ... DDR3 SDRAM Specifications and Conditions DD ≥ MIN Q/2 DD DDR3-1333 DDR3-1600 -15 -125E 10-10-10 10-10-10 11-11-11 1.5 1. 107 128 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...

  • Page 30

    ... Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Micron Technology, Inc., reserves the right to change products or specifications without notice. 30 2Gb: x4, x8, x16 DDR3 SDRAM Specifications and Conditions ...

  • Page 31

    ... Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Micron Technology, Inc., reserves the right to change products or specifications without notice. 31 2Gb: x4, x8, x16 DDR3 SDRAM Specifications and Conditions ...

  • Page 32

    ... Enabled Enabled, off Enabled, off 8 8 None None All All n/a n/a Micron Technology, Inc., reserves the right to change products or specifications without notice. 32 2Gb: x4, x8, x16 DDR3 SDRAM Specifications and Conditions Precharge DD Quiet Standby Active Power- Current Down Current 1 n/a HIGH ...

  • Page 33

    ... Repeat sub-loop 0, use BA[2: ODT = 1 Repeat sub-loop 0, use BA[2: ODT = 0 Repeat sub-loop 0, use BA[2: ODT = 0 Repeat sub-loop 0, use BA[2: ODT = 1 Repeat sub-loop 0, use BA[2: ODT = 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. 33 2Gb: x4, x8, x16 DDR3 SDRAM Specifications and Conditions ...

  • Page 34

    ... Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Micron Technology, Inc., reserves the right to change products or specifications without notice. 34 2Gb: x4, x8, x16 DDR3 SDRAM Specifications and Conditions ...

  • Page 35

    ... Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Repeat sub-loop 0, use BA[2: Micron Technology, Inc., reserves the right to change products or specifications without notice. 35 2Gb: x4, x8, x16 DDR3 SDRAM Specifications and Conditions ...

  • Page 36

    ... Self Refresh Current Normal Temperature Extended Temperature Range T = 0°C to 85° LOW Off, CK and CK# = LOW n/a n/a n/a n/a n/a n/a n/a n/a Mid-level Mid-level Mid-level Mid-level Mid-level Enabled Enabled, mid-level Enabled, mid-level n/a 36 2Gb: x4, x8, x16 DDR3 SDRAM Specifications and Conditions ...

  • Page 37

    ... Self Refresh Current Normal Temperature Extended Temperature Range T = 0°C to 85° n/a n/a disabled (normal) enabled (extended) disabled 37 2Gb: x4, x8, x16 DDR3 SDRAM Specifications and Conditions 6ET: Self Refresh Current Range = 0°C to 95° n/a n/a disabled t RFC. Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

  • Page 38

    ... Repeat sub-loop 11 use BA[2: Repeat sub-loop 10, use BA[2: Repeat sub-loop 11 use BA[2: Repeat cycle 3 × nFAW + 4 × nRRD until 4 × nFAW - 1, if needed Micron Technology, Inc., reserves the right to change products or specifications without notice. 38 2Gb: x4, x8, x16 DDR3 SDRAM Specifications and Conditions ...

  • Page 39

    ... ated by 2%; and I 6 and I 7 must be derated > 85° 2N must be derated by 2%; I 2Px must be derated by 30%; and I DD 80%. 39 2Gb: x4, x8, x16 DDR3 SDRAM Specifications DD DDR3-1600 Units 100 TBD mA 130 TBD mA n/a n/a mA 130 TBD mA 155 TBD mA n/a n/a ...

  • Page 40

    ... ated by 2%; and I 6 and I 7 must be derated > 85° 2N must be derated by 2%; I 2Px must be derated by 30%; and I DD 80%. 40 2Gb: x4, x8, x16 DDR3 SDRAM Specifications DD DDR3-1600 Units 80 TBD mA 90 TBD mA 120 TBD mA 105 TBD mA 115 TBD mA 150 TBD ...

  • Page 41

    ... ated by 2%; and I 6 and I 7 must be derated > 85° 2N must be derated by 2%; I 2Px must be derated by 30%; and I DD 80%. 41 2Gb: x4, x8, x16 DDR3 SDRAM Specifications DD DDR3-1600 Units 80 TBD mA 90 TBD mA 105 TBD mA 115 TBD mA 12 TBD mA 35 TBD ...

  • Page 42

    ... Externally generated peak noise (noncommon mode around the V V REF 2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifica- tions if the DRAM induces additional AC noise greater than 20 MHz in frequency REF level. Externally generated peak noise (noncommon mode × ...

  • Page 43

    ... Input low AC voltage: Logic 0 Input low AC voltage: Logic 0 Notes: 1. All voltages are referenced to V slew rates and setup/hold times are specified at the DRAM ball inputs. 2. Input setup timing parameters ( 3. Input hold timing parameters ( 4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is 900mV (peak-to-peak) ...

  • Page 44

    ... DDR3-800 DDR3-1066 (see Figure 14 on page 45) 0.67 Vns DD (see Figure 15 on page 45) 0.67 Vns SS 44 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC levels with ringback IH DDR3-1333 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.5 Vns 0.4 Vns ...

  • Page 45

    ... Q 0.25 Vns SS SS Maximum amplitude / Maximum amplitude 45 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC DDR3-1066 DDR3-1333 0.4V 0.4V 0.4V 0.4V 0.19 Vns 0.15 Vns 0.19 Vns 0.15 Vns Overshoot area Time (ns) Undershoot area Time (ns) Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

  • Page 46

    ... expected to track variations extended range (±175mV) is allowed only for the clock, and this Vix X Micron Technology, Inc., reserves the right to change products or specifications without notice. 46 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC Max n/a –200 )- REF × ...

  • Page 47

    ... V V PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/ (MIN) SEH Q SEH (MAX) SEL 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and DQS V SEL Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...

  • Page 48

    ... MAX (MAX) ) MAX half cycle t DVAC) for CK - CK# and DQS - DQS# Slew Rate (V/ns) >4.0 4.0 3.0 2.0 1.9 1.6 1.4 1.2 1.0 <1.0 48 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and CK# DQS - DQS# t DVAC t DVAC (ps IHDIFF AC ILDIFF 350mV 300mV ...

  • Page 49

    ... MIN and the first crossing Measured Edge From Rising V REF Falling V REF Rising MAX IL DC Falling MIN 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and MIN. Setup ( MAX (see Figure 19 on page 50 Hold ( REF (see Figure 19 on page 50). REF To Calculation MIN MIN - Δ ...

  • Page 50

    ... Nominal Slew Rate Definition for Single-Ended Input Signals Setup Hold PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN Electrical Specifications – DC and AC ΔTFS ΔTRH ΔTFH Micron Technology, Inc., reserves the right to change products or specifications without notice. 50 2Gb: x4, x8, x16 DDR3 SDRAM ΔTRS MIN MIN IH ...

  • Page 51

    ... From Rising MAX IL DIFF Falling MIN IH DIFF ΔTF DIFF Micron Technology, Inc., reserves the right to change products or specifications without notice. 51 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC ) MAX and MIN. The nominal slew IH DIFF ( ) MIN and IH DIFF To Calculation MIN IH ...

  • Page 52

    ... R and R TT 60PD120 40Ω is made and R TT 40PD80 30Ω is made and R TT 30PD60 20Ω is made and R TT 20PD40 52 2Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics turned off turned off TT PU Nom Max See Table 33 on page Refer to “ODT Sensitivity” on page 53 if ...

  • Page 53

    ... ODT Sensitivity If either the temperature or voltage changes after I/O calibration, the tolerance limits listed in Table 32 on page 52 and Table 33 can be expected to widen according to Tables 34 and 35 on page 54. PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 2Gb: x4, x8, x16 DDR3 SDRAM V Min OUT 0.2 × ...

  • Page 54

    ... Timing reference point ZQ RZQ = 240Ω End Point Definition Extrapolated point at V Extrapolated point at V Extrapolated point at V Extrapolated point at V Extrapolated points ODTL 4, or CWN 8 CWN 54 2Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics Max dT × |DT × |DV| RZQ/( 12) TT Q(@ calibration) and Max 1.5 ...

  • Page 55

    ... RZQ/2 (120Ω AOF Begin point: Rising edge CK# defined by the end point of ODTL off CK CK# t AON End point: Extrapolated point 2Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics 50mV 100mV 50mV 100mV 50mV 100mV 50mV 100mV 200mV , AOF End point: Extrapolated point ...

  • Page 56

    ... End point: Extrapolated point at V Begin point: Rising edge CK# defined by the end point of ODTL CNW t ADC RTT NOM RTT WR 56 2Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics V t AOFPD End point: Extrapolated point RTT NOM ODTL 8 CWN CWN t ADC V _ RTT ...

  • Page 57

    ... Chip in drive mode Output driver OUT 1%) and is actually 34.3Ω ± Micron Technology, Inc., reserves the right to change products or specifications without notice. 57 2Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance is defined by the value of the external ON and R ) are defined turned off OUT ...

  • Page 58

    ... ON 34PD DD 0.5 × 30.5 DD 0.8 × 30.5 DD 0.2 × 30.5 ON 34PU DD 0.5 × 30.5 DD 0.8 × 20 2Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance Nom Max 1.0 1.1 1.0 1.1 1.0 1.4 1.0 1.4 1.0 1.1 1.0 1.1 n 100 X = 1.575V, and Table 42 on page 59 for ...

  • Page 59

    ... DD Min dTH × |Δ dVH × |ΔV| ON dTM × |Δ dVM × |ΔV| ON dTL × |Δ dVL × |Δ 2Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance Nom Min 8.8 7.9 21.9 19.7 35.0 24.8 35.0 24.8 21.9 19.7 8.8 7.9 ...

  • Page 60

    ... C Min dTH × |Δ dVH × |ΔV| ON dTM × |Δ dVM × |ΔV| ON dTL × |Δ dVL × |Δ 2Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance Max 1.5 0.13 1.5 0.13 1.5 0.13 Nom Max 1.0 1.1 1.0 1.1 1.0 1 ...

  • Page 61

    ... Table 47: 40Ω Output Driver Voltage and Temperature Sensitivity Output Characteristics and Operating Conditions The DRAM uses both single-ended and differential output drivers. The single-ended output driver is summarized in Table 48 while the differential output driver is summa- rized in Table 49 on page 62. Table 48: ...

  • Page 62

    ... Output Characteristics and Operating Conditions Symbol I OZ SRQ DIFF ) = –0.2 × OHDIFF OLDIFF AC MM PUPD Output Q/ 2Gb: x4, x8, x16 DDR3 SDRAM Min Max – 150 V + 150 REF REF +0.2 × –0.2 × –10 +10 (V Q/2) via 25Ω resistor TT DD MAX output ...

  • Page 63

    ... Output Characteristics and Operating Conditions Q REF 25Ω Q DQS DQS# Timing reference point RZQ = 240Ω 2Gb: x4, x8, x16 DDR3 SDRAM X Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. MAX output DIFF MAX MIN ...

  • Page 64

    ... Nominal Slew Rate Definition for Single-Ended Output Signals PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN Output Characteristics and Operating Conditions ( OL AC Slew Rates (Linear Signals) Measured Edge From Rising Falling Δ 2Gb: x4, x8, x16 DDR3 SDRAM ) and for single-ended signals, as shown Calculation Δ ...

  • Page 65

    ... Nominal Differential Output Slew Rate Definition for DQS, DQS# PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN Output Characteristics and Operating Conditions ( ) and Rates (Linear Signals) Edge From Rising V ( OLDIFF Falling V ( OHDIFF ΔTF DIFF 65 2Gb: x4, x8, x16 DDR3 SDRAM ( ) for differential signals, as shown in Table 51 AC Measured To Calculation ) OHDIFF OHDIFF ) OLDIFF AC ...

  • Page 66

    ... Supported CWL settings t Notes: 1. REFI depends The CL and CWL settings result in CL and CWL requirement settings need to be fulfilled. 3. Reserved settings are not allowed. PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 2Gb: x4, x8, x16 DDR3 SDRAM -25E 5-5-5 Symbol Min Max t RCD 12.5 – ...

  • Page 67

    ... CK (AVG) Reserved t CK (AVG) 1.875 <2 OPER t CK requirements. When making a selection of Micron Technology, Inc., reserves the right to change products or specifications without notice. 67 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables -187 8-8-8 Min Max Units Notes 15 – – ns 52.5 – ...

  • Page 68

    ... CK (AVG) Reserved t CK (AVG) 1.5 <1.875 OPER t CK requirements. When making a selection of Micron Technology, Inc., reserves the right to change products or specifications without notice. 68 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables -15 10-10-10 Min Max Units Notes 15 – – – ...

  • Page 69

    ... CK (AVG) Reserved t CK (AVG) 1.25 <1 10 OPER t CK requirements. When making a selection of Micron Technology, Inc., reserves the right to change products or specifications without notice. 69 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables -125 11-11-11 Min Max Units Notes 13.125 – ns 13.125 – ns 48.75 – ...

  • Page 70

    Table 56: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 76 Parameter Clock period average 0°C to 85°C C DLL disable mode T = >85°C ...

  • Page 71

    Table 56: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 76 Parameter Data setup time to Base (specification) DQS, DQS V/ns REF Data setup ...

  • Page 72

    Table 56: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 76 Parameter DLL locking time CTRL, CMD, ADDR Base (specification) setup to CK,CK V/ns ...

  • Page 73

    Table 56: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 76 Parameter ZQCL command: Long POWER-UP and RESET calibration time operation Normal operation ZQCS command: Short calibration ...

  • Page 74

    Table 56: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 76 Parameter CKE MIN pulse width Command pass disable delay Power-down entry to power-down exit timing Begin ...

  • Page 75

    Table 56: Electrical Characteristics and AC Operating Conditions (Sheet Notes: 1–8 apply to the entire table; notes appear on page 76 Parameter R synchronous turn-on delay TT R synchronous turn-off delay TT R turn-on from ODTL on ...

  • Page 76

    ... CL (AVG) are the average half clock period over any 200 the maximum deviation in the clock period from the aver- JIT PER the amount the clock period can deviate from one JIT CC 76 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables ≤ T +95°C and +1.5V ±0.075V output buffer selection ...

  • Page 77

    ... SDRAM input clock). 22. Single-ended signal parameter. 23. The DRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by the actual jitter error when input clock jitter is pres- ent, even when within specification. This results in each parameter becoming larger. ...

  • Page 78

    ... JIT 40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT turn-off time maximum is when the DRAM buffer is in High-Z. The ODT refer- ence load is shown in Figure 22 on page 54. This output load is used for ODT timings (see Figure 29 on page 63). ...

  • Page 79

    ... IH) nominal slew rate for a rising signal is defined as the slew rate between the ( ) MAX and the first crossing MIN and the first crossing of V REF DDR3-1066 DDR3-1333 125 65 275 190 200 140 79 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables t IS (base) + Δ t IS. For a valid tran for some time ]/V [ ...

  • Page 80

    ... DDR3 SDRAM Speed Bin Tables ( ) = 175mV IL AC REF DC 1.6 V/ns 1.4 V/ns 1.2 V/ns Δ t Δ t Δ t Δ t Δ t Δ ...

  • Page 81

    ... AC t Slew Rate (V/ns) VAC at 175mV (ps) >2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 <0.5 81 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables t VAC at 150mV (ps Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...

  • Page 82

    ... VAC for IS (Command and Address – Clock REF region Nominal slew rate t VAC Δ MAX REF ΔTF 82 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables VAC Nominal slew rate REF region Δ MIN - V ( Setup slew rate IH AC REF = rising signal ΔTR Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...

  • Page 83

    ... IH REF Nominal slew rate Δ MAX REF Hold slew rate = falling signal ΔTR Micron Technology, Inc., reserves the right to change products or specifications without notice. 83 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Nominal slew rate REF region Δ MIN - REF DC = Δ ...

  • Page 84

    ... AC Tangent line t VAC Setup slew rate rising signal ΔTF Setup slew rate falling signal Micron Technology, Inc., reserves the right to change products or specifications without notice. 84 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables VAC Tangent line REF region ΔTR ...

  • Page 85

    ... Tangent line (V Hold slew rate = rising signal Tangent line (V Hold slew rate = falling signal Micron Technology, Inc., reserves the right to change products or specifications without notice. 85 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Nominal line Tangent line Nominal line ΔTR ...

  • Page 86

    ... MAX and the first crossing MIN and the first crossing of V REF DDR3-1066 DDR3-1333 25 – 100 65 86 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables t DS. For a valid transition, the input t )/ for some time VAC (see Table ]/ the time of the rising clock transi- ...

  • Page 87

    ... DQS, DQS# Differential Slew Rate 2.0 V/ns 1.8 V/ Δ Δ Δ Δ Δ –4 0 – –10 8 –2 8 –8 87 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables 1.6 V/ns 1.4 V/ns 1.2 V/ Δ Δ Δ Δ Δ –1 –10 7 –2 15 –11 –16 – ...

  • Page 88

    ... VAC at 175mV (ps) Slew Rate (V/ns) >2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 <0.5 88 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables [ ]) for Valid Transition AC t VAC at 150mV (ps) Min Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

  • Page 89

    ... DS (DQ – Strobe region Nominal slew rate t VAC Δ MAX REF Setup slew rate = rising signal ΔTF 89 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables VAC Nominal slew rate REF region Δ MIN - REF DC = ΔTR Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

  • Page 90

    ... DH REF Nominal slew rate Δ MAX REF Hold slew rate = falling signal ΔTR Micron Technology, Inc., reserves the right to change products or specifications without notice. 90 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Nominal slew rate REF region Δ MIN - REF DC = Δ ...

  • Page 91

    ... PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/ (DQ – Strobe Nominal to AC Tangent line t VAC Setup slew rate = rising signal ΔTF Setup slew rate = falling signal 91 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables VAC line Tangent line REF region ΔTR Tangent line ( MIN - ...

  • Page 92

    ... Tangent line (V Hold slew rate = rising signal Tangent line (V Hold slew rate = falling signal Micron Technology, Inc., reserves the right to change products or specifications without notice. 92 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Nominal line Tangent line Nominal line ΔTF ...

  • Page 93

    ... Micron Technology, Inc., reserves the right to change products or specifications without notice. 93 2Gb: x4, x8, x16 DDR3 SDRAM Commands BA [2:0] An A12 A10 code Row address (RA RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU ©2006 Micron Technology, Inc. All rights reserved. ...

  • Page 94

    ... Burst READs or WRITEs cannot be terminated or interrupted. MRS (fixed) and OTF BL/BC are defined in MR0. 9. The purpose of the NOP command is to prevent the DRAM from registering any unwanted commands. A NOP will not terminate an operation that is executing. 10. The DES and NOP commands perform similarly. ...

  • Page 95

    ... The ZQCL command triggers the calibration engine inside the DRAM. After calibration is achieved, the cali- brated values are transferred from the calibration engine to the DRAM I/O, which are reflected as updated R The DRAM is allowed a timing window defined by either the full calibration and transfer of values ...

  • Page 96

    ... DDR3_D4.fm - Rev G 2/09 EN CKE Previous Next Cycle Cycle CS# RAS# CAS# WE CKE Prev Next Symbol Cycle Cycle CS# RAS# CAS# WE WRS4 WRS8 WRAP WRAPS4 WRAPS8 2Gb: x4, x8, x16 DDR3 SDRAM BA [3:0] An A12 RFU RFU RFU RFU RFU RFU H BA [3:0] An A12 RFU RFU RFU ...

  • Page 97

    ... However, the precharge period is determined by the last PRECHARGE command issued to the bank. REFRESH REFRESH is used during normal operation of the DRAM and is analogous to CAS#- before-RAS# (CBR) refresh or auto refresh. This command is nonpersistent must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a “ ...

  • Page 98

    ... DRAM is targeted, but not guaranteed, to operate similarly to the normal mode with a few notable exceptions: • The DRAM supports only one value of CAS latency ( and one value of CAS WRITE latency (CWL = 6). • DLL disable mode affects the read data clock-to-data strobe relationship ( ...

  • Page 99

    ... After 4. Self refresh may be exited when the clock is stable with the new frequency for After 5. The DRAM will be ready for its next command in the DLL disable mode after the greater of appropriate timings met as well. Figure 41: DLL Enable Mode to DLL Disable Mode ...

  • Page 100

    ... Due to latency counter and timing restrictions, only and CWL = 6 are DIS t DQSCK starts from the rising clock edge Micron Technology, Inc., reserves the right to change products or specifications without notice. 100 2Gb: x4, x8, x16 DDR3 SDRAM Commands Td0 Te0 Tf0 Tg0 t DLLK ...

  • Page 101

    ... Access window of DQS from CK, CK# Input Clock Frequency Change When the DDR3 SDRAM is initialized, it requires the clock to be stable during most normal states of operation. This means that after the clock frequency has been set to the stable state, the clock period is not allowed to deviate except what is allowed for by the clock jitter and spread spectrum clocking (SSC) specifications ...

  • Page 102

    ... ODT signal must be continuously registered LOW ensuring R an off state. If the R charge power-down mode, R tered either LOW or HIGH in this case. PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN and R _ must remain in an off state. After the DLL lock time, the DRAM Tc1 Ta0 Tb0 Tc0 t CH ...

  • Page 103

    ... Note that nonstandard ODT schemes are required. The memory controller using the write leveling procedure must have adjustable delay settings on its DQS strobe to align the rising edge of DQS to the clock at the DRAM pins. This is accomplished when the DRAM asynchronously feeds back the CK status via the DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the DQS strobe until a CK transition from “ ...

  • Page 104

    ... Notes: 1. Expected usage if used during write leveling: Case 1 may be used when DRAM are on a dual-rank module and on the rank not being levelized or on any rank of a module not being levelized on a multislotted system. Case 2 may be used when DRAM are on any rank of a module not being levelized on a multislotted system ...

  • Page 105

    ... Write Leveling Procedure A memory controller initiates the DRAM write leveling mode by setting MR1[ “1,” assuming the other programable features (MR0, MR1, MR2, and MR3) are first set and the DLL is fully reset and locked. The DQ balls enter the write leveling mode going from a High-Z state to an undefined driving state, so the DQ bus should not be driven ...

  • Page 106

    ... Differential DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. The solid line represents DQS; the dotted line represents DQS#. 5. DRAM drives leveling feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ are driven LOW and remain in this state throughout the leveling procedure. ...

  • Page 107

    ... Tb0 Tc0 NOP NOP NOP NOP t AOF (MIN) ODTL off _ TT NOM t AOF (MAX Indicates a Break in Time Scale 107 2Gb: x4, x8, x16 DDR3 SDRAM Tc1 Tc2 Td0 Td1 Te0 NOP MRS NOP Valid NOP t MRD MR1 Valid t MOD Undefined Driving Mode Transitioning Micron Technology, Inc ...

  • Page 108

    ... Q may be applied before or at the same time DLLK (512) cycles of clock input are required to lock the DLL DLLK and ZQ have been satisfied, the DDR3 SDRAM will be ready for nor- INIT 108 2Gb: x4, x8, x16 DDR3 SDRAM Q during power ramp also High-Z). All TT ≤ ...

  • Page 109

    ... BA2 = L BA2 = 500µs (MIN) t XPR t MRD MR2 MR3 DRAM ready for external commands Micron Technology, Inc., reserves the right to change products or specifications without notice. 109 2Gb: x4, x8, x16 DDR3 SDRAM Operations Tc0 Tb0 Ta0 MRS MRS ZQCL Code Code Code ...

  • Page 110

    ... Down Mode” on page 153). 4. For a CAS latency change, The controller must also wait (excluding NOP and DES), as shown in Figure 50 on page 111. The DRAM requires in order to update the requested features, with the exception of DLL RESET, which requires additional time. Until assumed unavailable ...

  • Page 111

    ... Mode” on page 153). Mode Register 0 (MR0) The base register, MR0, is used to define various DDR3 SDRAM modes of operation. These definitions include the selection of a burst length, burst type, CAS latency, oper- ating mode, DLL RESET, write recovery, and precharge power-down mode, as shown in Figure 51 on page 112 ...

  • Page 112

    ... Reserved 112 2Gb: x4, x8, x16 DDR3 SDRAM Address bus Mode register 0 (MR0 Burst Length 0 0 Fixed BL8 (on-the-fly via A12 Fixed BC4 (chop Reserved CAS Latency M3 READ Burst Type Reserved 0 Sequential (nibble Interleaved Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

  • Page 113

    ... DLLK) clock cycles before a READ command can be issued. This DQSCK timings (ns) and rounding up a noninteger value to the next integer: WR (cycles [ns]/ CK [ns]). Micron Technology, Inc., reserves the right to change products or specifications without notice. 113 2Gb: x4, x8, x16 DDR3 SDRAM Operations Burst Type = Interleaved (Decimal) Notes ...

  • Page 114

    ... The CL is defined by MR0[6:4], as shown in Figure 51 on page 112. CAS latency is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The CL can be set 10. DDR3 SDRAM do not support half-clock latencies. Examples and are shown in Figure 52 internal READ command is registered at clock edge n, and the CAS latency is m clocks, the data will be available nominally coincident with clock edge ...

  • Page 115

    ... RZQ/8 (30Ω [NOM]) n Reserved Reserved Reserved Reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 115 2Gb: x4, x8, x16 DDR3 SDRAM value (ODT), WRITE LEVELING, POSTED t t MRD and MOD before Address bus Mode register 1 (MR1 ODS DLL ...

  • Page 116

    ... When the TDQS function is disabled, the DM function is provided, and the TDQS# ball is not used. The TDQS function is available in the x8 DDR3 SDRAM configuration only and must be disabled via the mode register for the x4 and x16 configurations. PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D4 ...

  • Page 117

    ... AL is supported to make the command and data bus efficient for sustainable band- widths in DDR3 SDRAM. MR1[4, 3] define the value shown in Figure 54 on page 118. MR1[4, 3] enable the user to program the DDR3 SDRAM with With this feature, the DDR3 SDRAM enables a READ or WRITE command to be issued after the ACTIVATE command for that bank prior to ACTIVATE to READ or WRITE + AL ≥ ...

  • Page 118

    ... Mode register set 3 (MR3) Dynamic ODT M6 M10 Disabled: Manual disabled Enabled: Automatic 0 1 RZQ RZQ Reserved 118 2Gb: x4, x8, x16 DDR3 SDRAM T11 T12 T13 NOP NOP NOP Indicates a Break in Transitioning Data Time Scale t t MRD and MOD before initiating a subse- A10 ...

  • Page 119

    ... In the disabled mode, SRT requires the user to ensure the DRAM never exceeds a T When SRT is enabled, the DRAM self refresh is changed internally from 1X to 2X, regard- less of the case temperature. This enables the user to operate the DRAM beyond the standard 85° ...

  • Page 120

    ... SRT or the ASR to ensure self refresh is performed at the 2X rate. SRT forces the DRAM to switch the internal self refresh rate from 1X to 2X. Self refresh is performed at the 2X refresh rate regardless of the case temperature. ASR automatically switches the DRAM’s internal self refresh rate from 1X to 2X. However, while in self refresh mode, ASR enables the refresh rate to automatically adjust between over the supported temperature range ...

  • Page 121

    ... MPR register, and bits 1 and 0 determine which mode the MPR is placed in. The basic concept of the multipurpose register is shown in Figure 58 on page 122. If MR3[ “0,” then the MPR access is disabled, and the DRAM operates in normal mode. However, if MR3[ “1,” then the DRAM no longer outputs normal read data but outputs MPR data as defined by MR3[0, 1]. If MR3[ equal to “ ...

  • Page 122

    ... MR3[ (MPR on) DQ, DM, DQS, DQS# Normal operation, no MPR transaction All subsequent READs come from the DRAM memory array All subsequent WRITEs go to the DRAM memory array Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

  • Page 123

    ... RFU n/a n/a n/a n/a n/a n/a 123 2Gb: x4, x8, x16 DDR3 SDRAM Burst Order and Data Pattern Burst order Predefined pattern Burst order Predefined pattern Burst order Predefined pattern n/a n/a n/a n/a n/a n/a ...

  • Page 124

    Figure 59: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout T0 Ta0 Tb0 Tb1 CK# CK READ 1 Command PREA MRS NOP MOD Bank address 3 Valid 0 2 A[1: ...

  • Page 125

    Figure 60: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout Tc0 CK# CK READ 1 READ 1 Command PREA MRS MOD t CCD Bank address 3 Valid Valid ...

  • Page 126

    Figure 61: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble Tc0 CK# CK READ 1 READ 1 Command PREA MRS CCD t MOD Bank address 3 Valid Valid ...

  • Page 127

    Figure 62: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble Tc0 CK# CK READ 1 READ 1 Command PREA MRS MOD t CCD Bank address 3 Valid Valid ...

  • Page 128

    ... A[1: (data burst order is fixed starting at nibble) – (for BL8, burst order is fixed – A12 = 1 (use BL8) • After CL, the DRAM bursts out the predefined read calibration pattern ( • The memory controller repeats the calibration reads until read data capture at memory controller is optimized • ...

  • Page 129

    ... All devices connected to the DQ bus should be High-Z during calibration. ACTIVATE Before any READ or WRITE commands can be issued to a bank within the DRAM, a row in that bank must be opened (activated). This is accomplished via the ACTIVATE command, which selects both the bank and the row to be activated. ...

  • Page 130

    ... T4 NOP ACT NOP NOP Row Bank ACT NOP ACT NOP Row Row Bank b Bank c t FAW 130 2Gb: x4, x8, x16 DDR3 SDRAM t CCD (MIN). t FAW (MIN) param T10 NOP NOP NOP t RCD Indicates a Break in Time Scale T9 T10 T11 T19 ACT NOP ...

  • Page 131

    ... data-out from column n. 2. Subsequent elements of data-out appear in the programmed order following DO n. DQS, DQS# is driven by the DRAM along with the output data. The initial low state on DQS and HIGH state on DQS# is known as the READ preamble ( DQS and the HIGH state on DQS#, coincident with the last data-out element, is known as the READ postamble ( commands have been initiated, the DQ will go High-Z ...

  • Page 132

    ... However, the precharge period will be determined by the last PRECHARGE command issued to the bank. If A10 is HIGH when a READ command is issued, the READ with auto precharge function is engaged. The DRAM starts an auto precharge operation on the rising edge which RTP cycles after the READ command. DRAM support a Figure 75 on page 136) ...

  • Page 133

    Figure 67: Consecutive READ Bursts (BL8 CK# CK Command 1 READ NOP NOP NOP t CCD Bank, Address 2 Col n DQS, DQS Notes: 1. NOP commands are shown for ease ...

  • Page 134

    Figure 69: Nonconsecutive READ Bursts CK# CK Command READ NOP NOP NOP NOP Bank a, Address Col DQS, DQS# DQ Notes ...

  • Page 135

    Figure 71: READ (BC4) to WRITE (BC4) OTF CK# CK Command 1 READ NOP NOP NOP READ-to-WRITE command delay = CCD Bank, Address 2 Col n DQS, ...

  • Page 136

    Figure 73: READ to PRECHARGE (BC4 CK# CK Command READ NOP NOP NOP NOP Bank a, Address Col n t RTP DQS, DQS RAS Figure 74: READ to PRECHARGE ( ...

  • Page 137

    ... DDR3_D4.fm - Rev G 2/09 EN 2Gb: x4, x8, x16 DDR3 SDRAM t DQSQ of the crossing point of DQS, DQS#. t DQSCK of the clock crossing point. The data Q). Prior to data output from the DRAM RPRE. This is known as the READ preamble. t RPST, is one half clock from the last DQS, DQS# transition. ...

  • Page 138

    Figure 76: Data Output Timing – DQSQ and Data Valid Window T0 T1 CK# CK Command 1 READ NOP Bank, Address 2 Col n DQS, DQS (last data valid (first data no longer valid) All ...

  • Page 139

    ... LZ (DQS) MIN and HZ (DQS) MIN are not tied (DQS) MAX and HZ (DQS) MAX are not tied to Micron Technology, Inc., reserves the right to change products or specifications without notice. 139 2Gb: x4, x8, x16 DDR3 SDRAM (DQ) or begins driving LZ (DQS (DQS), LZ (DQ) by measuring the ...

  • Page 140

    ... Single-ended signal, provided as background information DQS# Single-ended signal, provided as background information DQS - DQS# Resulting differential signal relevant for t RPST specification PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/ RPRE begins t RPRE CK CK RPST begins 140 2Gb: x4, x8, x16 DDR3 SDRAM RPRE ends RPST RPST ends Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...

  • Page 141

    ... WR has been met, as shown in Figure 90 on page 148 and Figure WTR and WR starting time may vary depending on the mode register settings 141 2Gb: x4, x8, x16 DDR3 SDRAM t DQSS (MIN) and Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...

  • Page 142

    ... WPST specification PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/ WPRE begins t WPRE signal relevant for t WPRE specification t WPST T1 t WPST begins 142 2Gb: x4, x8, x16 DDR3 SDRAM WPRE ends WPST ends Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

  • Page 143

    ... DQSH t DSS t DSS DQSS t WPRE t DQSH t DQSL t DQSH t DQSL t DSS t DSS Micron Technology, Inc., reserves the right to change products or specifications without notice. 143 2Gb: x4, x8, x16 DDR3 SDRAM Operations NOP NOP NOP t DSH t DSH t WPST t DQSL t DQSH t DQSL t DQSH t DQSL DSH ...

  • Page 144

    Figure 84: Consecutive WRITE (BL8) to WRITE (BL8 CK# CK Command 1 WRITE NOP NOP NOP t CCD Address 2 Valid DQS, DQS Notes: 1. NOP commands are shown for ease ...

  • Page 145

    Figure 86: Nonconsecutive WRITE to WRITE CK# CK Command WRITE NOP NOP NOP NOP Address Valid WL = CWL + DQS, DQS Notes ( data-in ...

  • Page 146

    Figure 88: WRITE to READ (BC4 Mode Register Setting CK# CK Command 1 WRITE NOP NOP Address 3 Valid DQS, DQS Notes: 1. NOP commands are shown for ease of illustration; other commands may be ...

  • Page 147

    Figure 89: WRITE (BC4 OTF) to READ (BC4 OTF CK# CK Command 1 WRITE NOP NOP NOP Address 3 Valid DQS, DQS Notes: 1. NOP commands are shown for ease of ...

  • Page 148

    ... WR) is referenced from the first rising clock edge after the last t WR specifies the last burst WRITE cycle until the PRECHARGE Micron Technology, Inc., reserves the right to change products or specifications without notice. 148 2Gb: x4, x8, x16 DDR3 SDRAM Operations T9 T10 T11 ...

  • Page 149

    ... The WRITE preamble and postamble are also shown. One clock prior to data input to the DRAM, DQS must be HIGH and DQS# must be LOW. Then for a half clock, DQS is driven LOW (DQS# is driven HIGH) during the WRITE preamble, be kept LOW by the controller after the last data is written to the DRAM during the WRITE postamble, Data setup and hold times are shown in Figure 93 on page 149 ...

  • Page 150

    ... First and foremost, the clock must be stable (meeting specifications) when self refresh mode is entered. If the clock remains stable and the frequency is not altered while in self refresh mode, then the DRAM is allowed to exit self refresh mode after than when CKE was registered LOW) ...

  • Page 151

    ... ODT can be a “Don’t Care.” must be met, and no data bursts can be in progress. t ISXR at Tc1. Micron Technology, Inc., reserves the right to change products or specifications without notice. 151 2Gb: x4, x8, x16 DDR3 SDRAM Tc0 Tc1 Td0 Te0 Valid NOP 5 ...

  • Page 152

    ... Extended Temperature Usage Micron’s DDR3 SDRAM support the optional extended temperature range of 0°C to 95° Thus, the SRT and ASR options must be used at a minimum. C The extended temperature range DRAM must be refreshed externally at 2X (double refresh) anytime the case temperature is above 85°C (and does not exceed 95°C). The external refreshing requirement is accomplished by reducing the refresh period from 64ms to 32ms ...

  • Page 153

    ... READ operation as well as synchronous ODT operation. During power-down entry, if any bank remains open after all in-progress commands are complete, the DRAM will be in active power-down mode. If all banks are closed after all in-progress commands are complete, the DRAM will be in precharge power-down mode. ...

  • Page 154

    ... ODT must valid state but all other input signals are a “Don’t Care.” If RESET# goes LOW during power-down, the DRAM will switch out of power-down mode and go into the reset state. After CKE is registered LOW, CKE must ...

  • Page 155

    ... PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/ NOP t CPDED t IH tCKEmin t PD Exit power-down NOP t CPDED Exit power-down 155 2Gb: x4, x8, x16 DDR3 SDRAM T4 T5 Ta0 NOP NOP NOP t CKE (MIN) tCKEmin mode Indicates a Break in Time Scale T4 Ta Ta1 Valid 1 NOP NOP ...

  • Page 156

    ... WRPDEN t CK earlier if BC4MRS. Micron Technology, Inc., reserves the right to change products or specifications without notice. 156 2Gb: x4, x8, x16 DDR3 SDRAM Operations Ta7 Ta8 Ta9 Ta10 NOP NOP CPDED t PD Power-down or self refresh entry Indicates a Break In Transitioning Data Time Scale Ta7 ...

  • Page 157

    ... Ta0 t CL NOP NOP t CPDED RFC (MIN RFC, CKE must remain HIGH until Micron Technology, Inc., reserves the right to change products or specifications without notice. 157 2Gb: x4, x8, x16 DDR3 SDRAM Operations Ta7 Tb0 Tb1 Tb2 Tb3 NOP NOP NOP NOP t IS ...

  • Page 158

    ... CL NOP NOP t CPDED t IS tCKE NOP NOP t CPDED t IS Micron Technology, Inc., reserves the right to change products or specifications without notice. 158 2Gb: x4, x8, x16 DDR3 SDRAM Operations Don’t Care Don’t Care ©2006 Micron Technology, Inc. All rights reserved. ...

  • Page 159

    ... HIGH. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power up were executed (see Figure 106 on page 160). All refresh counters on the DRAM are reset, and data stored in the DRAM is assumed unknown after RESET# has gone LOW. PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D4 ...

  • Page 160

    ... Code Code BA0 = L BA0 = H BA1 = H BA1 = H BA2 = L BA2 = L t MRD t XPR t MRD MR2 MR3 DRAM ready for external commands 160 2Gb: x4, x8, x16 DDR3 SDRAM Tb0 Tc0 Ta0 Valid Valid Valid MRS MRS ZQCL Code Code Code Code A10 = H BA0 = H BA0 = L ...

  • Page 161

    ... On-Die Termination (ODT) ODT is a feature that enables the DRAM to enable/disable and turn on/off termination resistance for each DQ, DQS, DQS#, and DM for the x4 and x8 configurations (and TDQS, TDQS# for the x8 configuration, when enabled). ODT is applied to each DQ, UDQS, UDQS#, LDQS, LDQS#, UDM, and LDM signal for the x16 configuration. ...

  • Page 162

    ... The R mentioned. DDR3 SDRAM supports multiple R can and RZQ is 240Ω. R the DRAM is initialized, calibrated, and not performing read access or when it is not in self refresh mode. Write accesses use R during writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 81 on page 164). ...

  • Page 163

    ... Dynamic ODT In certain application cases, and to further enhance signal integrity on the data bus desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command, essentially changing the ODT termination on the fly. With dynamic ODT (R dynamic ODT (R to nominal ODT (R ...

  • Page 164

    ... Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 164 2Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT ...

  • Page 165

    Figure 108: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 CK# CK Command NOP NOP NOP NOP WRS4 Address Valid ODTH4 ODT ODTL DQS, DQS# DQ Notes: 1. Via MRS ...

  • Page 166

    Figure 110: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 CK# CK NOP WRS8 NOP Command ODTL CNW Address Valid ODTL ON ODT R TT DQS, DQS# DQ Notes: 1. Via ...

  • Page 167

    ... AON (MIN) ODTL 4 CWN NOM _ is enabled Micron Technology, Inc., reserves the right to change products or specifications without notice. 167 2Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT T10 NOP NOP NOP NOP ODTL off t ADC (MIN NOM t ADC (MAX Transitioning and R _ are enabled ...

  • Page 168

    ... Since write latency is made up of CAS WRITE latency (CWL) and ADDITIVE latency (AL), the AL programmed into the mode register (MR1[4, 3]) also applies to the ODT signal. The DRAM’s internal ODT signal is delayed a number of clock cycles defined by the AL relative to the external ODT signal. Thus ODTL on = CWL + and ODTL off = CWL + ...

  • Page 169

    Table 84: Synchronous ODT Parameters Symbol Description ODTL on ODT synchronous turn-on delay ODTL off ODT synchronous turn-off delay ODTH4 ODT minimum HIGH time after ODT assertion or WRITE (BC4) ODTH8 ODT minimum HIGH time after WRITE (BL8) t AON ...

  • Page 170

    Figure 114: Synchronous ODT (BC4 CK# CK CKE Command NOP NOP NOP NOP NOP ODTH4 ODT ODTL Notes NOM 2. ODT ...

  • Page 171

    ... ODT Off During READs As the DDR3 SDRAM cannot terminate and drive at the same time least one-half clock cycle before the READ preamble by driving the ODT ball LOW (if either R amble as shown in the example in Figure 115 on page 172. Note: ODT may be disabled earlier and enabled later than shown in Figure 115 on page 172. ...

  • Page 172

    Figure 115: ODT During READs CK# CK Command READ NOP NOP NOP NOP Address Valid ODTL off = CWL + ODT DQS, DQS# DQ Notes: 1. ODT must be ...

  • Page 173

    ... Asynchronous ODT Mode Asynchronous ODT mode is available when the DRAM runs in DLL on mode and when either R precharged power-down standby (via MR0[12]). Additionally, ODT operates asynchro- nously when the DLL is synchronizing after being reset. See “Power-Down Mode” on page 153 for definition and guidance over power-down details. ...

  • Page 174

    Figure 116: Asynchronous ODT Timing with Fast ODT Transition CK# CK CKE ODT t AONPD (MIN Notes ignored. Table 85: Asynchronous ODT Timing Parameters for All ...

  • Page 175

    ... Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) There is a transition period around power-down entry (PDE) where the DRAM’s ODT may exhibit either synchronous or asynchronous behavior. This transition period occurs if the DLL is selected to be off when in precharge power-down mode by the setting MR0[12 ...

  • Page 176

    ... NOP ODT A synchronous DRAM NOM synchronous ODT B asynchronous or synchronous DRAM NOM asynchronous or synchronous ODT C asynchronous DRAM asynchronous Notes CWL = 5; ODTL off = Min Greater of: t Lesser of: AONPD (MIN) (1ns) or × ODTL AON (MIN) t Lesser of: AOFPD (MIN) (1ns) or × ODTL off CK + AOF (MIN) ...

  • Page 177

    ... Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) The DRAM’s ODT may exhibit either asynchronous or synchronous behavior during power-down exit (PDX). This transition period occurs if the DLL is selected to be off when in precharge power-down mode by setting MR0[12] to “0.” Power-down exit begins ...

  • Page 178

    ... NOM asynchronous t AOFPD (MAX) ODT B asynchronous or synchronous asynchronous NOM or synchronous ODT C synchronous DRAM synchronous Notes CWL = 5; ODTL off = Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 NOP NOP NOP NOP NOP NOP t XPDLL PDX transition period ODTL off + t AOF (MIN) t AOFPD (MAX) t AOFPD (MIN) ...

  • Page 179

    ... If the time in the precharge power down or idle states is very short (short CKE LOW pulse), the power-down entry and power-down exit transition periods will overlap. When overlap occurs, the response of the DRAM’ synchronous or asynchronous from the start of the power-down entry transition period to the end of the power-down exit transition period even if the entry period ends later than the exit period (see Figure 119 on page 180) ...

  • Page 180

    Figure 119: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping CK# CK Command REF NOP NOP NOP CKE t ANPD Short CKE LOW transition period (R Notes ...

  • Page 181

    ... PDF: 09005aef826aaadc/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN 2Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Micron Technology, Inc., reserves the right to change products or specifications without notice. 181 ...