MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 114

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Precharge Power-Down (Precharge PD)
CAS Latency (CL)
Figure 52: READ Latency
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
DQS, DQS#
DQS, DQS#
Command
Command
CK#
CK#
DQ
DQ
CK
CK
READ
READ
T0
T0
Notes:
NOP
NOP
T1
T1
The precharge PD bit applies only when precharge power-down mode is being used.
When MR0[12] is set to “0,” the DLL is off during precharge power-down providing a
lower standby current mode; however,
MR0[12] is set to “1,” the DLL continues to run during precharge power-down mode to
enable a faster exit of precharge power-down mode; however,
exiting (see “Power-Down Mode” on page 153).
The CL is defined by MR0[6:4], as shown in Figure 51 on page 112. CAS latency is the
delay, in clock cycles, between the internal READ command and the availability of the
first bit of output data. The CL can be set to 5, 6, 7, 8, 9, or 10. DDR3 SDRAM do not
support half-clock latencies.
Examples of CL = 6 and CL = 8 are shown in Figure 52. If an internal READ command is
registered at clock edge n, and the CAS latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 52 on page 66 through Table 54 on
page 68indicate the CLs supported at various operating frequencies.
1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible.
2. Shown with nominal
NOP
NOP
T2
T2
AL = 0, CL = 6
NOP
NOP
T3
T3
t
DQSCK and nominal
AL = 0, CL = 8
114
NOP
NOP
T4
T4
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
XPDLL must be satisfied when exiting. When
t
NOP
NOP
T5
T5
DSDQ.
2Gb: x4, x8, x16 DDR3 SDRAM
NOP
NOP
T6
T6
DI
n
t
XP must be satisfied when
©2006 Micron Technology, Inc. All rights reserved.
n + 1
Transitioning Data
DI
NOP
NOP
T7
T7
n + 2
DI
Operations
n + 3
DI
NOP
NOP
T8
T8
Don’t Care
n + 4
DI
DI
n