MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 177

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D5.fm - Rev G 2/09 EN
The DRAM’s ODT may exhibit either asynchronous or synchronous behavior during
power-down exit (PDX). This transition period occurs if the DLL is selected to be off
when in precharge power-down mode by setting MR0[12] to “0.” Power-down exit begins
t
registered HIGH.
The transition period is
ODT assertion during power-down exit results in an R
t
t
down exit may result in an R
ODTL off ×
ODTL off ×
If the AL has a large value, the uncertainty of the R
because ODTL on and ODTL off are derived from the WL, and WL is equal to CWL + AL.
Figure 118 on page 178 shows three different cases:
• ODT C: asynchronous behavior before
• ODT B: ODT state changes during the transition period, with
• ODT A: ODT state changes after the transition period with synchronous response
ANPD prior to CKE first being registered HIGH, and it ends
AONPD (MIN) and ODTL on ×
AONPD (MAX) and ODTL on ×
ODTL off ×
t
AOFPD (MAX)
t
t
CK +
CK +
t
CK +
t
t
t
AOF (MIN) or as late as the greater of
AOF (MAX). Table 86 on page 176 summarizes these parameters.
ANPD is equal to the greater of ODTL off + 1
t
AOF (MIN) and ODTL off ×
t
ANPD plus
TT
177
change as early as the lesser of
t
t
CK +
CK +
t
XPDLL.
t
t
AON (MIN) or as late as the greater of
AON (MAX). ODT de-assertion during power-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
ANPD
t
CK +
2Gb: x4, x8, x16 DDR3 SDRAM
TT
state becomes quite large. This is
TT
t
On-Die Termination (ODT)
AOF (MAX) greater than
t
AOFPD (MAX) and
change as early as the lesser of
t
XPDLL after CKE is first
t
t
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AOFPD (MIN) and
CK or ODTL on + 1
t
AOFPD (MIN) less than
t
CK.