MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 13

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Functional Block Diagrams
Figure 3:
Figure 4:
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D2.fm - Rev G 2/09 EN
RZQ
RZQ
V
V
SS
SS
A[14:0]
BA[2:0]
A[14:0]
BA[2:0]
ZQ
Q
ZQ
CK, CK#
Q
CK, CK#
RESET#
RESET#
RAS#
CAS#
RAS#
CAS#
WE#
ODT
WE#
CKE
A12
ODT
CS#
CKE
A12
CS#
18
18
512 Meg x 4 Functional Block Diagram
256 Meg x 8 Functional Block Diagram
Address
register
Address
register
Mode registers
Mode registers
Control
logic
Control
logic
18
18
15
15
Refresh
counter
Refresh
counter
ZQCL, ZQCS
ZQCL, ZQCS
DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally
configured as an 8-bank DRAM.
11
10
3
3
BC4 (burst chop)
OTF
BC4 (burst chop)
OTF
15
15
address
3
address
3
Row-
MUX
Row-
MUX
Column-
counter/
Column-
counter/
address
control
address
control
Bank
15
Bank
15
latch
logic
latch
logic
ZQ CAL
ZQ CAL
decoder
address
decoder
address
Bank 0
Bank 0
latch
row-
latch
row-
and
and
Bank 1
Bank 1
Bank 2
Bank 2
7
8
3
3
Bank 3
Bank 3
Bank 4
Bank 4
32,768
32,768
Bank 5
Bank 5
Bank 6
Columns 0, 1, and 2
Bank 6
Columns 0, 1, and 2
Bank 7
Bank 7
To pullup/pulldown
(32,768 x 256 x 32)
To ODT/output drivers
(32,768 x 128 x 64)
Sense amplifiers
Sense amplifiers
DM mask logic
DM mask logic
I/O gating
I/O gating
decoder
networks
Column
decoder
Memory
Column
memory
Bank 0
Bank 0
(x32)
array
8,192
(128
x64)
array
8,192
256
Bank 1
Bank 1
Bank 2
Bank 2
Bank 3
Bank 3
Bank 4
Bank 4
13
Bank 5
Bank 5
Bank 6
Bank 6
Bank 7
Bank 7
DM
32
64
BC4
OTF
BC4
OTF
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64
32
64
32
Columns 0, 1, and 2
Columns 0, 1, and 2
interface
interface
READ
CK, CK#
MUX
READ
FIFO
data
data
MUX
CK,CK#
and
FIFO
and
Data
Data
2Gb: x4, x8, x16 DDR3 SDRAM
Data
Data
8
4
8
4
lower nibble for BC4)
lower nibble for BC4)
(select upper or
(select upper or
Functional Block Diagrams
Column 2
Column 2
drivers
drivers
Write
WRITE
input
logic
input
and
and
logic
control
control
ODT
ODT
CK, CK#
drivers
CK,CK#
drivers
Read
READ
DLL
BC4
DLL
BC4
©2006 Micron Technology, Inc. All rights reserved.
DQS, DQS#
DQ[7:0]
DQS, DQS#
sw1
sw1
sw1
sw1
sw1
sw1
DQ[3:0]
R
R
V
R
V
V
TT
TT
R
DD
TT
DD
V
R
R
DD
V
V
TT
_
_
DD
TT
TT
_
DD
Q/2
DD
Q/2
NOM
NOM
Q/2
NOM
_
_
_
Q/2
NOM
Q/2
NOM
Q/2
NOM
DQ8
R
R
sw2
R
TT
TT
TT
R
sw2
sw2
sw2
sw2
R
R
sw2
_
_
TT
_
TT
TT
WR
WR
WR
_
_
_
WR
WR
WR
(1, 2)
(1, 2)
(1 . . . 8)
(1 . . . 4)
TDQS#
DQS/DQS#
DM/TDQS
(shared pin)
DQ[7:0]
DQ[3:0]
DQS, DQS#
DM