AD5381BST-3 Analog Devices Inc, AD5381BST-3 Datasheet - Page 16

• Manufacturer Part Number: AD5381BST-3
• Description: IC DAC 12BIT 40CH 3V 100-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD5381BST-3

• Design Resources: 40 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5381 (CN0010) AD5381 Channel Monitor Function (CN0013)
• Settling Time: 6µs
• Number Of Bits: 12
• Data Interface: Serial, Parallel
• Number Of Converters: 40
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 80mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• For Use With: EVAL-AD5381EB - BOARD EVAL FOR AD5381
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD5381
Mnemonic
PD
FIFO EN
DB9/(SPI/I
DB10/(SCLK/SCL)
DB11/(DIN/SDA)
2
C)
Function
Power-Down (Level Sensitive, Active High). PD is used to place the device in low power mode, where the analog
current consumption is reduced to 2 μA and the digital current consumption is reduced to 20 μA. In power-down
mode, all internal analog circuitry is placed in low power mode, and the analog output is configured as a high
impedance output or provides a 100 kΩ load to ground, depending on how the power-down mode is configured.
The serial interface remains active during power-down.
FIFO Enable (Level Sensitive, Active High). When connected to DVDD, the internal FIFO is enabled, allowing the user
to write to the device at full speed. FIFO is only available in parallel interface mode. The status of the FIFO EN pin is
sampled on power-up, and also following a CLEAR or RESET, to determine if the FIFO is enabled. In either serial or
I
Multifunction Input Pin. In parallel interface mode, this pin acts as DB9 of the parallel input data-word. In serial
interface mode, this pin acts as serial interface mode select. When serial interface mode is selected (SER/PAR = 1) and
this input is low, SPI mode is selected. In SPI mode, DB12 is the serial clock (SCLK) input and DB11 is the serial data
(DIN) input.
When serial interface mode is selected (SER/PAR = 1) and this input is high I
In this mode, DB12 is the serial clock (SCL) input and DB11 is the serial data (SDA) input.
Multifunction Input Pin. In parallel interface mode, this pin acts as DB10 of the parallel input data-word. In serial
interface mode, this pin acts as a serial clock input.
Serial Interface Mode. In serial interface mode, data is clocked into the shift register on the falling edge of SCLK.
This operates at clock speeds up to 50 MHz.
I
I
Multifunction Data Input Pin. In parallel interface mode, this pin acts as DB11 of the parallel input data-word.
Serial Interface Mode. In serial interface mode, this pin acts as the serial data input. Data must be valid on the falling
edge of SCLK.
I
2
2
2
2
C interface modes, the FIFO EN pin should be tied low.
C Mode. In I
C mode is compatible with both 100 kHz and 400 kHz operating modes.
C Mode. In I
2
2
C mode, this pin performs the SCL function, clocking data into the device. The data transfer rate in
C mode, this pin is the serial data pin (SDA) operating as an open-drain input/output.
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2
C Mode is selected.