AD5381BST-3 Analog Devices Inc, AD5381BST-3 Datasheet - Page 21

• Manufacturer Part Number: AD5381BST-3
• Description: IC DAC 12BIT 40CH 3V 100-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD5381BST-3

• Design Resources: 40 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5381 (CN0010) AD5381 Channel Monitor Function (CN0013)
• Settling Time: 6µs
• Number Of Bits: 12
• Data Interface: Serial, Parallel
• Number Of Converters: 40
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 80mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• For Use With: EVAL-AD5381EB - BOARD EVAL FOR AD5381
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE—GENERAL
The AD5381 is a complete, single-supply, 40-channel voltage
output DAC that offers 12-bit resolution. The part is available
in a 100-lead LQFP package and features both a parallel and
a serial interface. This product includes an internal, software
selectable, 1.25 V/2.5 V, 10 ppm/°C reference that can be used
to drive the buffered reference inputs; alternatively, an external
reference can be used to drive these inputs. Internal/external
reference selection is via the CR8 bit in the control register;
CR10 selects the reference magnitude if the internal reference
is selected. All channels have an on-chip output amplifier with
rail-to-rail output capable of driving 5 kΩ in parallel with a
200 pF load.
The architecture of a single DAC channel consists of a 12-bit
resistor-string DAC followed by an output buffer amplifier
operating at a gain of 2. This resistor-string architecture
guarantees DAC monotonicity. The 12-bit binary digital code
loaded to the DAC register determines at what node on the
string the voltage is tapped off before being fed to the output
amplifier. Each channel on these devices contains independent
offset and gain control registers that allow the user to digitally
trim offset and gain. These registers give the user the ability to
calibrate out errors in the complete signal chain, including the
DAC, using the internal m and c registers, which hold the
correction factors. All channels are double buffered, allow-
ing synchronous updating of all channels using the LDAC pin.
Figure 27 shows a block diagram of a single channel on the
AD5381. The digital input transfer function for each DAC
can be represented as
where:
x2 = the data-word loaded to the resistor string DAC.
x1 = the 12-bit data-word written to the DAC input register.
m = the gain coefficient (default is 0xFFE). The gain coefficient
is written to the 11 most significant bits (DB11 to DB1), the LSB
(DB0) of the data-word is a 0.
n = DAC resolution (n = 12 for AD5381).
c = the12-bit offset coefficient (default is 0x800).
INPUT DATA
x2 = [(m + 2)/ 2
×1 INPUT
m REG
c REG
REG
Figure 27. Single-Channel Architecture
×2
n
× x1] + (c – 2
DAC
REG
12-BIT
VREF
DAC
n – 1
)
AVDD
R
R
VOUT
Rev. B | Page 21 of 40
The complete transfer function for these devices can be
represented as
where:
x2 is the data-word loaded to the resistor string DAC. V
is externally applied to the DAC REFOUT/REFIN pin. For
specified performance, an external reference voltage of 2.5 V is
recommended for the AD5381-5, and 1.25 V for the AD5381-3.
DATA DECODING
The AD5381 contains a 12-bit data bus, DB11 to DB0. Depend-
ing on the value of REG1 and REG0 (see Table 11), this data is
loaded into the addressed DAC input registers, offset (c)
registers, or gain (m) registers. The format data, offset (c), and
gain (m) register contents are shown in Table 12 to Table 14.
Table 11. Register Selection
REG1
1
1
0
0
Table 12. DAC Data Format (REG1 = 1, REG0 = 1)
1111
1111
1000
1000
0111
0000
0000
Table 13. Offset Data Format (REG1 = 1, REG0 = 0)
1111
1111
1000
1000
0111
0000
0000
Table 14. Gain Data Format (REG1 = 0, REG0 = 1)
1111
1011
0111
0011
0000
VOUT = 2 × V
DB11 to DB0
REG0
1
0
1
0
1111
1111
0000
0000
1111
0000
0000
DB11 to DB0
DB11 to DB0
1111
1111
0000
0000
1111
0000
0000
1111
1111
1111
1111
0000
REF
Register Selected
Input Data Register (x1)
Offset Register (c)
Gain Register (m)
Special Function Registers (SFRs)
× x2/2
1111
1110
0001
0000
1111
0001
0000
1111
1110
0001
0000
1111
0001
0000
1110
1110
1110
1110
0000
n
DAC Output (V)
2 V
2 V
2 V
2 V
2 V
2 V
0
REF
REF
REF
REF
REF
REF
× (4095/4096)
× (4094/4096)
× (2049/4096)
× (2048/4096)
× (2047/4096)
× (1/4096)
Offset (LSB)
+2048
+2047
+1
0
–1
–2047
–2048
Gain Factor
1
0.75
0.5
0.25
0
AD5381
REF