AD5381BST-3 Analog Devices Inc, AD5381BST-3 Datasheet - Page 22

• Manufacturer Part Number: AD5381BST-3
• Description: IC DAC 12BIT 40CH 3V 100-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD5381BST-3

• Design Resources: 40 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5381 (CN0010) AD5381 Channel Monitor Function (CN0013)
• Settling Time: 6µs
• Number Of Bits: 12
• Data Interface: Serial, Parallel
• Number Of Converters: 40
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 80mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• For Use With: EVAL-AD5381EB - BOARD EVAL FOR AD5381
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD5381
ON-CHIP SPECIAL FUNCTION REGISTERS (SFR)
The AD5381 contains a number of special function registers
(SFRs), as outlined in Table 15. SFRs are addressed with
REG1 = REG0 = 0 and are decoded using Address Bits
A5 to A0.
Table 15. SFR Register Functions (REG1 = 0, REG0 = 0)
R/W
X
0
0
0
0
0
1
0
0
SFR COMMANDS
NOP (No Operation)
REG1 = REG0 = 0, A5 to A0 = 000000
Performs no operation but is useful in serial readback mode to
clock out data on D
low during a NOP operation.
Write CLR Code
REG1 = REG0 = 0, A5 to A0 = 000001
DB11 to DB0 = Contain the CLR data
Bringing the CLR line low or exercising the soft clear function
will load the contents of the DAC registers with the data con-
tained in the user configurable CLR register, and will set
VOUT0 to VOUT39 accordingly. This can be very useful for
setting up a specific output voltage in a clear condition. It is also
beneficial for calibration purposes; the user can load full scale
or zero scale to the clear code register and then issue a hard-
ware or software clear to load this code to all DACs, removing
the need for individual writes to each DAC. Default on power-
up is all zeros.
A5
0
0
0
0
0
0
0
0
0
A4
0
0
0
0
0
0
0
0
0
A3
0
0
0
1
1
1
1
1
1
OUT
for diagnostic purposes. BUSY pulses
A2
0
0
0
0
0
1
1
0
1
A1
0
0
1
0
0
0
0
1
1
0
1
0
0
1
0
0
0
1
A0
Function
NOP (No Operation)
Write CLR Code
Soft CLR
Soft Power-Down
Soft Power-Up
Control Register Write
Control Register Read
Monitor Channel
Soft Reset
Rev. B | Page 22 of 40
Soft CLR
REG1 = REG0 = 0, A5 to A0 = 000010
DB11 to DB0 = Don’t Care
Executing this instruction performs the CLR, which is func-
tionally the same as that provided by the external CLR pin. The
DAC outputs are loaded with the data in the CLR code register.
It takes 35 μs to fully execute the SOFT CLR, as indicated by the
BUSY low time.
Soft Power-Down
REG1 = REG0 = 0, A5 to A0 = 001000
DB11 to DB0 = Don’t Care
Executing this instruction performs a global power-down
feature that puts all channels into a low power mode that
reduces the analog supply current to 2 μA max and the digi-
tal current to 20 μA max. In power-down mode, the output
amplifier can be configured as a high impedance output or
provide a 100 kΩ load to ground. The contents of all internal
registers are retained in power-down mode. No register can be
written to while in power-down.
Soft Power-Up
REG1 = REG0 = 0, A5 to A0 = 001001
DB11 to DB0 = Don’t Care
This instruction is used to power up the output amplifiers and
the internal reference. The time to exit power-down is 8 μs.
The hardware power-down and software function are internally
combined in a digital OR function.
Soft RESET
REG1 = REG0 = 0, A5 to A0 = 001111
DB11 to DB0 = Don’t Care
This instruction is used to implement a software reset. All
internal registers are reset to their default values, which corre-
spond to m at full scale and c at zero scale. The contents of the
DAC registers are cleared, setting all analog outputs to 0 V. The
soft reset activation time is 135 μs.