DSPB56362AG120 Freescale Semiconductor, DSPB56362AG120 Datasheet - Page 147

• Manufacturer Part Number: DSPB56362AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56362AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (126 kB)
• On-chip Ram: 42kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 120MHz
• Mips: 120
• Device Input Clock Speed: 120MHz
• Ram Size: 42KB
• Program Memory Size: 90KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Instruction Set Architecture: Modified Harvard
• Device Million Instructions Per Second: 120 MIPS
• Maximum Clock Frequency: 120 MHz
• Program Memory Type: Flash
• Data Ram Size: 42 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SPI, I2C, ESAI, SHI
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Index
A
ac electrical characteristics 3
Address Trace mode 3, 38, 41
applications 5
arbitration bus timings 41
B
bootstrap ROM 3
Boundary Scan (JTAG Port) timing diagram 72
bus
bus acquisition timings 42
bus release timings 43, 44
C
clock
clocks
D
data memory expansion 4
DAX 4, 2, 16
dc electrical characteristics 2
Debug support 3
design considerations
Freescale Semiconductor
address 2
data 2
multiplexed 2
non-multiplexed 2
external 4
operation 5
internal 4
DSP56362 Technical Data, Rev. 4
Digital Audio Transmitter 4, 16
DRAM
DRAM controller 4
DSP programming 6
E
electrical design considerations 3
Enhanced Serial Audio Interface 4
ESAI 4, 2
ESSI
EXTAL jitter 5
external bus control 6, 7
external bus synchronous timings (SRAM access)
electrical 3
PLL 4, 5
power consumption 3
thermal 1
out of page
out of page and refresh timings
Page mode
Page mode timings
refresh access 38
receiver timing 66, 67
timings 62
transmitter timing 65
read access 36
wait states selection guide 28
write access 37
11 wait states 32
15 wait states 33
4 wait states 28
8 wait states 30
read accesses 27
wait states selection guide 19
write accesses 26
1 wait state 19
2 wait states 21
3 wait states 22
4 wait states 24
Index-1