0W633-001-XTP ON Semiconductor, 0W633-001-XTP Datasheet - Page 13

• Manufacturer Part Number: 0W633-001-XTP
• Description: IC AUDIO PROCESSOR AD/DA 57LFBGA
• Manufacturer: ON Semiconductor
• Series: BelaSigna® 250r
• Type: Floating Pointr

Specifications of 0W633-001-XTP

• Interface: I²C, I²S, PCM, SPI, UART
• Clock Rate: 50MHz
• On-chip Ram: 42kB
• Voltage - I/o: 1.0V, 2.0V
• Voltage - Core: 1.00V, 2.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 57-LFBGA
• Package: 57CABGA
• Numeric And Arithmetic Format: Fixed-Point
• Ram Size: 16 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Non-volatile Memory: -

Internal Power Supplies
supplies. Each supply requires an external decoupling capacitor, even if the supply is not used externally. Decoupling capacitors
should be placed as close as possible to the power pads. Further details on these critical signals are provided in Table 6.
Non−critical signals are outlined in Table 7.
Table 6. CRITICAL SIGNALS
Table 7. NON−CRITICAL SIGNALS
VBAT
VREG, VDBL
AGND
VDDO / VDDC
GNDO / GNDC
AI0, AI1 / LOUT,
AI2, AI3
AIR
AO0, AO1
RCVR0+, RCVR0−,
RCVR1+, RCVR1−
AOR
RCVRGND
EXT_CLK
AI_RC
CAP0, CAP1
DEBUG_TX, DEBUG_RX
TWSS_SDA, TWSS_CLK
GPIO[14..0]
GPIO[15]
UART_RX, UART_TX
PCM_FRAME, PCM_CLK,
PCM_OUT, PCM_IN
I2S_INA, I2S_IND, I2S_FA,
I2S_FD, I2S_OUTA, I2S_OUTD
UCLK
LSAD[5..0]
SPI_CLK, SPI_CS,
SPI_SERI, SPI_SERO
Power management circuitry in BelaSigna 250 generates separate digital (VDDC) and analog (VREG, VDBL) regulated
Pin Name
Pin Name
Power supply
Internal regulator for analog sections
Analog ground return
Internal regulator for digital sections
(pads and core)
Digital ground return (pads and core)
Microphone inputs
Input stage reference voltage
Analog audio output
Direct digital audio output
Output stage reference voltage
Output stage ground return
External clock input / internal clock
output
Infrared receiver input
Internal charge pump − capacitor connection
Debug port
TWSS port
General−purpose I/O
General−purpose I/O
Determines voltage mode during boot. For 1.8 V
operation, should be connected to DGND.
General−purpose UART
Pulse code modulation port
I
Programmable clock output
Low−speed A/D converters
Serial peripheral interface port
Connect to EEPROM
2
Description
S compatible port
Description
http://onsemi.com
13
Place 1 mF (min) decoupling capacitor close to pin. Connect
negative terminal of capacitor to DGND plane.
Place separate 1 mF decoupling capacitors close to each pin. Con-
nect negative capacitor terminal to AGND. Keep away from digital
traces and output traces. VREG may be used to generate micro-
phone bias. VDBL shall not be used to supply external circuitry.
Connect to AGND plane.
Place 10 mF decoupling capacitor close to pin. Connect negative
terminal of capacitor to DGND (Unique pin on the WLCSP option).
Connect to digital ground.
Keep as short as possible. Keep away from all digital traces and
audio outputs. Avoid routing in parallel with other traces. Connect
unused inputs to AGND.
Connect to AGND. If no analog ground plane, should share trace
with microphone grounds to star point.
Keep away from microphone inputs.
Keep away from analog traces, particularly microphone inputs.
Route corresponding traces as differential pair; route parallel to each
other and approximately the same length.
Connect to star point. Share trace with power amplifier (if present).
Connect to star point. Keep away from analog inputs.
Minimize trace length. Keep away from analog signals. If possible,
surround with digital ground.
If used, minimize trace length to photodiode.
Not available on the WLCSP or CABGA option
Place 100 nF capacitor close to pins
Not critical − Connect to test points
Not critical
Not critical
Not critical
Not critical
Not critical − Keep away from analog signals.
Not critical
Not critical −
If used, keep away from analog inputs/outputs
Not critical
Not critical
Routing Guideline
Routing Guideline