0W633-001-XTP ON Semiconductor, 0W633-001-XTP Datasheet - Page 3

• Manufacturer Part Number: 0W633-001-XTP
• Description: IC AUDIO PROCESSOR AD/DA 57LFBGA
• Manufacturer: ON Semiconductor
• Series: BelaSigna® 250r
• Type: Floating Pointr

Specifications of 0W633-001-XTP

• Interface: I²C, I²S, PCM, SPI, UART
• Clock Rate: 50MHz
• On-chip Ram: 42kB
• Voltage - I/o: 1.0V, 2.0V
• Voltage - Core: 1.00V, 2.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 57-LFBGA
• Package: 57CABGA
• Numeric And Arithmetic Format: Fixed-Point
• Ram Size: 16 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Non-volatile Memory: -

Electrical Performance Specifications
1.8 V supply voltage. BelaSigna 250 was running in high voltage mode (VDDC = 1.8 V). The system clock (SYS_CLK) was
set to 5.12 MHz and a sampling frequency of 16 kHz was used with MCLK was set to 1.28 MHz.
OVERALL
VREG (1 mF External Capacitor)
VDBL (1 mF External Capacitor)
VDDC (1 mF External Capacitor)
VDDC (1 mF External Capacitor)
POWER−ON−RESET (POR)
Supply voltage
Current consumption
Regulated voltage output
Regulator PSRR
Load current
Load regulation
Line regulation
Regulated doubled voltage output
Regulator PSRR
Load current
Load regulation
Line regulation
Digital supply voltage output
Regulator PSRR
Load current
Load regulation
Line regulation
POR startup voltage
POR shutdown voltage
Table 2. ELECTRICAL SPECIFICATIONS
3. Audio performance will be degraded below 1.05 V.
4. Measured with a = 12 dB input signal.
5. Input stage delay is inversely proportional to sampling frequency.
6. Max voltage should be limited to 2.2 V peak regardless of VDDC. Protection diodes will be enabled above this voltage.
The parameters in Table 2 do not vary with WOLA filterbank configuration. The tests were performed at 20°C with a clean
Parameters marked as screened are tested on each chip. Other parameters are qualified but not tested on every part.
Description
VDDC
VDDC
V
VDDC
VDBL
LOAD
LOAD
LOAD
LINE
LINE
LINE
REG_PSRR
Symbol
VDDC
VDBL
V
I
I
I
V
SHUTDOWN
LOAD
LOAD
LOAD
I
BAT
REG
BAT
STARTUP
PSRR
REG
REG
REG
PSRR
REG
REG
REG
SYS_CLK = 1.28 MHz,
sample rate = 16 kHz
5.12 MHz, 16 kHz
19.2 MHz, 16 kHz
49.152 MHz, 16 kHz
49.152 MHz, 48 kHz
1 kHz
1 kHz
LV mode (VREG)
DV mode (VDBL)
LV mode; 1 kHz
DV mode; 1 kHz
All modes
LV mode
DV mode
LV mode
DV mode
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Conditions
3
(Note 3)
0.95
0.78
0.76
Min
0.9
1.9
0.9
1.8
50
45
20
40
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1.00
0.83
0.81
Typ
650
120
150
1.8
2.0
1.0
2.0
1.5
10
13
55
11
50
28
48
1
5
−
2
−
5
−
5
5
Max
1.05
0.88
0.86
200
250
2.0
2.1
1.1
2.2
3.5
20
10
10
10
10
−
−
−
−
−
2
5
2
−
−
mV/mA
mV/mA
mV/mA
mV/mA
Units
mV/V
mV/V
mV/V
mV/V
mA
mA
mA
mA
mA
mA
mA
mA
dB
dB
dB
dB
V
V
V
V
V
V
V
Screened
√
√
√
√
√
√
√