ADSP-2181BST-133 Analog Devices Inc, ADSP-2181BST-133 Datasheet - Page 10

• Manufacturer Part Number: ADSP-2181BST-133
• Description: IC DSP CONTROLLER 16BIT 128TQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2181BST-133

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 33.3MHz
• Non-volatile Memory: External
• On-chip Ram: 80kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Device Core Size: 16b
• Architecture: Enhanced Harvard
• Format: Fixed Point
• Clock Freq (max): 33.3MHz
• Mips: 33.3
• Device Input Clock Speed: 33.3MHz
• Ram Size: 80KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Lead Free Status / RoHS Status: Not Compliant

ADSP-2181
If Go Mode is enabled, the ADSP-2181 will not halt program
execution until it encounters an instruction that requires an
external memory access.
If the ADSP-2181 is performing an external memory access
when the external device asserts the BR signal, then it will not
three-state the memory interfaces or assert the BG signal until
the processor cycle after the access completes. The instruction
does not need to be completed when the bus is granted. If a
single instruction requires two external memory accesses, the
bus will be granted between the two accesses.
When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program
execution from the point where it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
The BGH pin is asserted when the ADSP-2181 is ready to
execute an instruction, but is stopped because the external bus
is already granted to another device. The other device can re-
lease the bus by deasserting bus request. Once the bus is re-
leased, the ADSP-2181 deasserts BG and BGH and executes
the external memory access.
Flag I/O Pins
The ADSP-2181 has eight general purpose programmable in-
put/output flag pins. They are controlled by two memory
mapped registers. The PFTYPE register determines the direc-
tion, 1 = output and 0 = input. The PFDATA register is used to
read and write the values on the pins. Data being read from a
pin configured as an input is synchronized to the ADSP-2181’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.
In addition to the programmable flags, the ADSP-2181 has
five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and
FL2. FL0-FL2 are dedicated output flags. FLAG_IN and
FLAG_OUT are available as an alternate configuration of
SPORT1.
INSTRUCTION SET DESCRIPTION
The ADSP-2181 assembly language instruction set has an
algebraic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of the
processor’s unique architecture, offers the following benefits:
• The algebraic syntax eliminates the need to remember cryptic
• Every instruction assembles into a single, 24-bit word that can
• The syntax is a superset ADSP-2100 Family assembly lan-
• Sixteen condition codes are available. For conditional jump,
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
execute in a single instruction cycle.
guage and is completely source and object code compatible
with other family members. Programs may need to be relo-
cated to utilize on-chip memory and conform to the ADSP-
2181’s interrupt vector and reset vector map.
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
–10–
• Multifunction instructions allow parallel execution of an
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The ADSP-2181 has on-chip emulation support and an ICE-
Port, a special set of pins that interface to the EZ-ICE. These
features allow in-circuit emulation without replacing the target
system processor by using only a 14-pin connection from the
target system to the EZ-ICE. Target systems must have a 14-pin
connector to accept the EZ-ICE ’s in-circuit probe, a 14-pin plug.
The ICE-Port interface consists of the following ADSP-2181 pins:
EBR
EBG
ERESET
These ADSP-2181 pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pull-
down resistors. The traces for these signals between the ADSP-
2181 and the connector must be kept as short as possible, no
longer than three inches.
The following pins are also used by the EZ-ICE:
BR
GND
The EZ-ICE uses the EE (emulator enable) signal to take con-
trol of the ADSP-2181 in the target system. This causes the
processor to use its ERESET, EBR and EBG pins instead of the
RESET, BR and BG pins. The BG output is three-stated.
These signals do not need to be jumper-isolated in your system.
The EZ-ICE connects to the target system via a ribbon cable
and a 14-pin female plug. The ribbon cable is 10 inches in
length with one end fixed to the EZ-ICE. The female plug is
plugged onto the 14-pin connector (a pin strip header) on the
target board.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown in
Figure 7. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE probe onto the 14-pin
connector.
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
Figure 7. Target Board Connector for EZ-ICE
EMS
EINT
ECLK
KEY (NO PIN)
BG
RESET
RESET
ELOUT
GND
EBG
EBR
EE
ELIN
ELOUT
EE
11
13
1
3
5
9
7
TOP VIEW
12
14
10
2
4
6
8
BG
BR
EMS
EINT
ELIN
ECLK
ERESET
REV. D